Neuromorphic computing is a recent class of brain-inspired high-performance computer platforms and algorithms involving biologically-inspired models adopting hardware implementation in integrated circuits. The neuromorphic computing applications have provoked the rise of highly connected neurons and synapses in analog circuit systems that can be used to solve today's challenging machine learning problems. In conjunction with biologically plausible learning rules, such as the Hebbian learning and memristive devices, biologically-inspired spiking neural networks are considered the next-generation neuromorphic hardware construction blocks that will enable the deployment of new analogin situlearning capable and energetic efficient brain-like devices. These features are envisioned for modern mobile robotic implementations, currently challenging to overcome the pervasive von Neumann computer architecture. This study proposes a new neural architecture using the spike-time-dependent plasticity learning method and step-forward encoding algorithm for a self tuning neural control of motion in a joint robotic arm subjected to dynamic modifications. Simulations were conducted to demonstrate the proposed neural architecture's feasibility as the network successfully compensates for changing dynamics at each simulation run.

A Kalman filter can be used to fill space–state reconstruction dynamics based on knowledge of a system and partial measurements. However, its performance relies on accurate modeling of the system dynamics and a proper characterization of the uncertainties, which can be hard to obtain in real-life scenarios. In this work, we explore how the values of a Kalman gain matrix can be estimated by using spiking neural networks through a combination of biologically plausible neuron models with spike-time-dependent plasticity learning algorithms. The performance of proposed neural architecture is verified with simulations of some representative nonlinear systems, which show promising results. This approach traces a path for its implementation in neuromorphic analog hardware that can learn and reconstruct partial and changing dynamics of a system without the massive power consumption that is typically needed in a Von Neumann-based computer architecture.

This article proposes a decentralized controller for differential mobile robots, providing autonomous navigation and obstacle avoidance by enforcing a formation toward trajectory tracking. The control system relies on dynamic modeling, which integrates evasion forces from obstacles, formation forces, and path-following forces. The resulting control loop can be seen as a dynamic extension of the kinematic model for the differential mobile robot, producing linear and angular velocities fed to the mobile robot’s kinematic model and thus passed to the low-level wheel controller. Using the Lyapunov method, the closed-loop stability is proven for the non-collision case. Experimental and simulated results that support the stability analysis and the performance of the proposed controller are shown.

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated spike-timing-dependent plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness in the shared synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130 nm process. The article’s main goal is to provide the basic building blocks for deep neural networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.

Se presenta un controlador descentralizado para robots móviles diferenciales, que provee navegación autónoma y evasión de obstáculos, que simultáneamente puede forzar una formación deseada, mientras se realiza seguimiento de trayectoria. El controlador está basado en modelado dinámico, integrando fuerzas de evasión de los obstáculos, fuerzas de formación, y fuerzas para el seguimiento de trayectoria. El lazo de control representa, por lo tanto, una extensión dinámica del modelo cinemático del robot móvil diferencial, generando velocidades lineales y angulares que alimentan al modelo cinemático del robot móvil. Usando teoría de Lyapunov, se prueba estabilidad del sistema en lazo cerrado para el caso libre de colisiones. Se presentan, para un caso de estudio, resultados experimentales que muestran correspondencia con los resultados teóricos.

Embedded systems increasingly require on-device deep learning, yet their processors must simultaneously handle real-time sensing, networking administration, and data control. Existing Field-Programmable Gate Array (FPGA) accelerators typically target peak per-operator throughput without addressing concurrent execution demands of real-time embedded platforms. This paper presents a systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted. Unlike traditional accelerators optimized for peak per-operator speed, this design prioritizes asynchronous co-executionbetween the processing system (PS, the dual-core Cortex-A9) and the programmable logic (PL): The PL performs tiled matrix multiplication, while the PS executes preprocessing, orchestration, and I/O data concurrently, increasing effective end-to-end throughput regardless of the relative isolated performance of CPU and FPGA. The proposed module includes high-level-synthesis (HLS)-based matrix multiplication, activation functions, and Advanced eXtensible Interface (AXI)-Stream Direct Memory Access (DMA) interfaces, wrapped as custom PyTorch kernels under the PetaLinux operating system. The results obtained on the PYNQ-Z2 board show that, once the DMA transfer time is included in the measurement, the FPGA path does not surpass Cortex-A9 in isolated per-operator latencies across the evaluated range; the benefit lies instead in delegating the matrix compute to the fabric at low incremental power while the host CPU cores stay available for concurrent tasks. A concurrent workload sweep across matrix sizes from $8\times 8$ to $256\times 256$ confirms that the co-execution mode sustains 98–99% of available PS compute throughput compared with a constant ≈50% in single-core blocking mode; the difference is statistically significant for all evaluated sizes (see Mann–Whitney U: $U=25$, $p=3.97\times {10}^{-3}$, perfect discrimination, $n=5$). A fair dual-core CPU-only baseline attains comparable PS availability, so this figure reflects the dual-core scheduling that co-execution enables rather than a per-operator advantage of the fabric; the accelerator’s distinct role is to perform the matrix arithmetic off the general-purpose cores at low incremental power. The design occupies only 8% of available look-up tables (LUTs) and 5% of digital signal processing (DSP) blocks, maintains 1.69 W power with a junction temperature of 44.5 °C, and achieves 96.10% MNIST accuracy under fixed-point arithmetic.