Recently, machine learning (ML) methods have been used to create powerful language models for a broad range of natural language processing tasks. An important subset of this field is that of generating code of programming languages for automatic software development. This review provides a broad and detailed overview of studies for code generation using ML. We selected 37 publications indexed in arXiv and IEEE Xplore databases that train ML models on programming language data to generate code. The three paradigms of code generation we identified in these studies are description-to-code, code-to-description, and code-to-code. The most popular applications that work in these paradigms were found to be code generation from natural language descriptions, documentation generation, and automatic program repair, respectively. The most frequently used ML models in these studies include recurrent neural networks, transformers, and convolutional neural networks. Other neural network architectures, as well as non-neural techniques, were also observed. In this review, we have summarized the applications, models, datasets, results, limitations, and future work of 37 publications. Additionally, we include discussions on topics general to the literature reviewed. This includes comparing different model types, comparing tokenizers, the volume and quality of data used, and methods for evaluating synthesized code. Furthermore, we provide three suggestions for future work for code generation using ML.

As machine learning continues to find applications, extensive research is currently underway across various domains. This study examines the current methodologies of machine learning being investigated to optimize semiconductor manufacturing processes. Our research involved searching the SPIE Digital Library, IEEE Xplore, and ArXiv databases, identifying 58 publications in the field of machine learning-based semiconductor process optimization. These investigations employ machine learning techniques such as feature extraction, feature selection, neural network architecture, and are analyzed using different algorithms. These models find applications in advanced process control, virtual metrology, and quality control, critical aspects in semiconductor manufacturing for enhancing throughput and reducing production costs. We categorize the papers based on the methods and applications employed, summarizing the primary findings. Furthermore, we discuss the general conclusions of several studies. Overall, the reviewed literature suggests that machine learning-based semiconductor manufacturing is rapidly gaining popularity and advancing at a swift pace.

Advanced semiconductor manufacturing (SM) lies at the heart of advancing computer chip technology, aiming to produce more sophisticated and economically viable chips. These chips comprise many interconnected electrical components, notably transistors, forming complex electronic circuits. Central to this endeavor is the drive to minimize the size of these components, historically correlating with significant gains in power, performance, and area.¹ Leveraging wafer-manufacturing techniques, wherein multiple chips (also known as dies on wafer) are fabricated concurrently, further underscores the economic advantage of miniaturization. Patterning, the process of creating the structures on the chip that form and connect electrical devices, is therefore the key challenge for advanced SM.

As the semiconductor manufacturing process is moving towards the 3 nm node, there is a crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the integrated circuit (IC) devices. EPE is the most important metric that quantify the fidelity of fabricated patterns in multi-patterning processes, and it is the combination of overlay errors and critical dimension (CD) errors. Recent advances in machine learning have enabled many new possibilities to improve the performance and efficiency of EPE optimization techniques. In this paper, we conducted a survey of recent research work that applied machine learning/ deep learning techniques for the purposes of enhancing virtual overlay metrology, reducing overlay error, and improving mask optimization methods for EPE reduction. Thorough discussions about the objectives, datasets, input features, models, key findings, and limitations are provided. In general, the results of the review work show a great potential of machine learning techniques in aiding the improvement of EPE in the field of semiconductor manufacturing.

In semiconductor manufacturing, lithography has often been the manufacturing step defining t he s mallest possible pattern dimensions. In recent years, progress In semiconductor manufacturing, lithography has often been the manufacturing step defining t he s mallest possible pattern dimensions. In recent years, progress

Hardware implementation of neural networks is challenging due to varying application requirements. This often necessitates creating specific Field Programmable Gate Arrays (FPGA) configurations from scratch for each application. This paper proposes a flexible, self-supervised reconfigurable method to fit several application requirements by providing only the maximum available computational nodes a priori. The proposed method dynamically reconfigures the required number of hidden layers and nodes based on the application. The goal is to automatically determine the optimal Neural Network (NN) configuration through reconfigurability to achieve maximum accuracy. Optimality is demonstrated through minimum average power, average delay, and area overhead, as well as maximum throughput and accuracy. Experimental results show that the proposed approach significantly reduces the optimized architecture search cost (the number of online training iterations) and associated average power consumption for successive datasets/applications. The method’s effectiveness is shown both quantitatively and qualitatively, verified against the MNIST and CIFAR-10 classification problems. Our reconfigurable method demonstrates stable accuracy of 98.97% and 98.95% compared to state-of-the-art neural networks with fixed configurations (98.85% and 73.0% for MNIST and 93.47% and 70.21% for CIFAR-10, respectively). Additionally, the proposed method shows a 20.9% reduction in average power dissipation compared to state-of-the-art methods. Implemented and tested using VHDL and Altera FPGA, the results indicate resource utilization comparable with the state-of-the-art method. This reconfigurability is especially advantageous for IoT applications where power efficiency and adaptability to different tasks are critical.