To balance the instantaneous power difference between the pulsed output power and the constant input power of the pulse load power supply (PLPS), an active capacitor converter (ACC), which can compensate the pulsed current, is connected in parallel with the output of the dc–dc converter in the PLPS. In this article, based on the Fourier decomposition results of the load current, it is evident that the square waves have significant harmonic content. Hence, to provide the lower impedance at the frequencies of the high content harmonics in the load current, a virtual impedance that consisted of the multiple quasi-notch-filters is proposed to be in parallel at the port of the ACC for the suppression of output voltage drop and input current ripple. The virtual parallel impedance is implemented by the output voltage feedforward control of the ACC. The design considerations of the virtual parallel impedance are presented to ensure the stability of the PLPS. Finally, a synchronous rectifier buck converter with a bidirectional buck/boost converter is tested at the pulse repetition frequency of 100–300 Hz and the pulse duty cycle of 0.15 to verify the validity of the proposed control scheme.
1 November 2017 in IEEE Journal of Emerging and Selected Topics in Power Electronics
In order to overcome the drawbacks of conventional bridgeless SEPIC PFC circuits, an improved bridgeless SEPIC PFC circuit is introduced by adding an additional output diode and an inductor. The undesired capacitive coupling loop and the circulating loss are removed. Thus, the high efficiency can be achieved. The operation principle and design consideration of the proposed converter is introduced in detail. Furthermore, a novel control method is employed to control the CCM bridgeless SEPIC PFC circuit without input voltage sensing. Meanwhile the UCC28019-based modified hardware implementation circuit is designed and described. A 100-W prototype with 90-135 Vrms input line voltage and 60V output voltage is built and tested. The corresponding experiment shows that the validity of proposed circuit topology and control strategy. A peak efficiency of 94% and power factor above 0.99 are achieved under 65-kHz switching frequency operation condition.
28 April 2020 in IEEE Transactions on Industrial Electronics
Pulse train (PT) control strategy for boost power factor correction (PFC) converter operating in continuous conduction mode (CCM) is proposed and studied in this paper. Average current mode (ACM) control is usually utilized for CCM boost PFC converter. ACM controlled PFC converter suffers from poor dynamic response, due to its voltage control loop has to be designed with low bandwidth to minimize the effect of low-frequency output voltage ripple on the current control loop. Different from ACM control, the voltage control loop and current control loop of PT controlled PFC converter are decoupled, thus the effect of low frequency output voltage ripple on the current control loop is eliminated. Besides, PT modulation is utilized in the proposed controller to regulate the inductor current to follow the current reference. Thus, both high power factor and fast dynamic response can be achieved. The operation principle of PT controlled CCM boost PFC converter is analyzed, and a 300W prototype is built to verify the analysis results. The experimental results show that power factor of PT controlled PFC converter is higher than 0.998 and the dynamic response is significantly improved.
24 May 2018 in IEEE Transactions on Industrial Electronics
For single-inductor dual-output (SIDO) DC-DC converter operating in continuous conduction mode (CCM), load variation of one output will affect the voltage of the other output, i.e. there exists cross regulation between its two outputs. To suppress the cross regulation of SIDO DC-DC converter operating in CCM, a novel ripple based control technique, called as capacitor current ripple (CCR) control technique, is proposed in this paper. The operation principle of SIDO CCM buck converter and the proposed CCR control technique are presented. The small signal model of CCR controlled SIDO CCM buck converter is established by state space averaging method. Bode plots based on small signal model show that the proposed CCR controlled SIDO CCM buck converter significantly reduces cross regulation and improves the transient performance compared with peak current mode (PCM) controlled SIDO CCM buck converter. In addition, the effect of the variation of loads on the stability of the proposed CCR controlled SIDO CCM buck converter is analyzed by eigenvalue analysis. Finally, experimental results are provided to verify the analysis results.
14 June 2018 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Single-stage boost-LLC ac-dc converters are popularly utilized as the front-end stage of multichannel LED street-lighting drivers. Pulse frequency modulation (PFM) strategy with a duty cycle of 0.5 is commonly utilized in these ac-dc converters. However, PFM has the following drawbacks: 1) high bus voltage limits the ac input voltage range, which makes it only suitable for the input voltage range of 85~135 V and 2) the maximum bus voltage can reach up to three times of the minimum bus voltage, which increases the difficulty of the LLC design. This paper proposed a hybrid modulation strategy, which consists of a bus voltage control loop using asymmetric pulsewidth modulation and an output voltage control loop using PFM. The stable output voltage and the quasi-constant bus voltage can be simultaneously achieved. Furthermore, by increasing bus voltage ripple and employing the twin-bus configuration, the short-lifetime electrolytic capacitors are eliminated, and the efficiency of the total LED driver can be greatly improved. Therefore, universal-input operation, high efficiency, low cost, and long lifetime are the key innovations of the proposed solution. A universal-input 100-W prototype is built to demonstrate the feature of the proposed solution. The experimental results show that the converter achieves a peak efficiency of 92.5% at the input voltage of 130 V and a high power factor value of above 0.95 over the whole input voltage range. With the proposed modulation strategy, the maximum bus voltage is just 500 V under universal input voltage condition, which is greatly lower than that of the traditional PFM controlled boost-LLC converters.