Hierarchical interconnection networks (HINs) provide a framework for designing networks with reduced link cost by taking advantage of the locality of communication that exists in parallel applications. HINs employ multiple levels. Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs provide fault tolerance in the presence of some faulty nodes and/or links. Existing HINs can be broadly classified into two classes. those that use nodes and/or links replication and those that use standby interface nodes. The first class includes Hierarchical Cubic Networks, Hierarchical Completely Connected Networks, and Triple-based Hierarchical Interconnection Networks. The second HINs class includes Modular Fault-Tolerant Hypercube Networks and Hierarchical Fault-Tolerant Interconnection Network. This paper presents a review and comparison of the topological properties of both classes of HINs. The topological properties considered are network degree, diameter, cost and packing density. The outcome of this study show among all HINs two networks that is, the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH), belonging to the first HIN class provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n,n)provide the best packing density, that is, the smallest chip area required for VLSI implementation.

We present linear and nonlinear techniques for design exploration of an iterative algorithm. The nonlinear techniques allow control of processor workload and control of communication between processors. The algorithm considered is the Sunar-Koç optimal normal basis type II multiplication algorithm. Six systolic arrays are obtained. General formulas are provided for each design so that the operation of the system can be determined for a given GF(2 ^m ). The proposed architectures have been implemented using 45-nm CMOS technology and compared with published architectures. The results show that the proposed designs have at least 44.4% lower total computation time compared with the designs of all bit serial multipliers, while having slightly larger area delay product (ADP), up to 19.1%, compared with some of the bit serial multipliers and having smaller ADP values compared with most of the digit serial ones. Moreover, they have at least 46% lower power delay product compared with all bit serial and digit serial multipliers.

This paper introduces a lightweight, energy-efficient Number Theoretic Transform (NTT) implementation tailored for the ML-KEM scheme in post-quantum cryptography. Unlike prior efforts focusing mainly on multipliers and modular reduction, the proposed design emphasizes the address generator, a critical yet often overlooked component. A compact counter-based mechanism integrated with XOR logic and multiplexing eliminates large lookup tables, reduces redundant operations, and ensures efficient memory access for both NTT and INTT. The unified butterfly unit and a LUT-based modular reduction circuit enable multi-cycle modular operations without requiring digital signal processing (DSP) or block RAM (BRAM) resources. The complete architecture occupies only 147 slices and 557 LUTs, achieving very low power consumption. Implemented on a Virtex-7 platform, the design demonstrates up to 88.8% reduction in area, 22% decrease in dynamic power, and a 17.57× improvement in A²T efficiency compared with state-of-the-art implementations. These results highlight the significance of optimizing address generation to achieve compact, power-aware accelerators. The architecture’s elimination of memory-intensive components and reliance on LUT-based logic make it highly portable and suitable for resource-constrained devices.