Miguel Garcia-Bosque

Dr. Miguel Garcia-Bosque

Group of Electronic Design, University of Zaragoza, 50009 Zaragoza, Spain
orcid

Research Focus & Metrics

Academic Career Length

57Years (1970-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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12 November 2018 in IEEE Transactions on Instrumentation and Measurement
Verified
Journal Article
Closed access
MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
APAdrián Pérez
Adrián Pérez
CSCarlos Sanchez-Azqueta
Carlos Sanchez-Azqueta
CAConcepcion Aldea
Concepcion Aldea
SCSantiago Celma
Santiago Celma
In this paper, a new pseudorandom number generator (PRNG) based on the logistic map has been proposed. To prevent the system to fall into short period orbits as well as increasing the randomness of the generated sequences, the proposed algorithm dynamically changes the parameters of the chaotic system. This PRNG has been implemented in a Virtex 7 field-programmable gate array (FPGA) with a 32-bit fixed point precision, using a total of 510 lookup tables (LUTs) and 120 registers. The sequences generated by the proposed algorithm have been subjected to the National Institute of Standards and Technology (NIST) randomness tests, passing all of them. By comparing the randomness with the sequences generated by a raw 32-bit logistic map, it is shown that, by using only an additional 16% of LUTs, the proposed PRNG obtains a much better performance in terms of randomness, increasing the NIST passing rate from 0.252 to 0.989. Finally, the proposed bitwise dynamical PRNG is compared with other chaos-based realizations previously proposed, showing great improvement in terms of resources and randomness.

21 March 2017 in Sensors
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Journal Article
Open access
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MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
APAdrián Pérez
Adrián Pérez
CSCarlos Sanchez-Azqueta
Carlos Sanchez-Azqueta
SCSantiago Celma
Santiago Celma
In this work, we used a sensor-based True Random Number Generator in order to generate keys for a stream cipher based on a recently published hybrid algorithm mixing Skew Tent Map and a Linear Feedback Shift Register. The stream cipher was implemented and tested in a Field Programmable Gate Array (FPGA) and was able to generate 8-bit width data streams at a clock frequency of 134 MHz, which is fast enough for Gigabit Ethernet applications. An exhaustive cryptanalysis was completed, allowing us to conclude that the system is secure. The stream cipher was compared with other chaotic stream ciphers implemented on similar platforms in terms of area, power consumption, and throughput.

1 September 2020
Verified
Conference Paper
Closed access
MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
GDG. Diez-Senorans
G. Diez-Senorans
CSC. Sanchez-Azqueta
C. Sanchez-Azqueta
SCS. Celma
S. Celma
During the last years, Physically Unclonable Functions (PUFs) have become a very important research area in the field of hardware security due to their capability of generating volatile secret keys as well as providing a low-cost authentication. In this paper, an introduction to Physically Unclonable Functions is given, including their definition, properties and applications. Finally, as an example of how to design a PUF, the general structure of a ring oscillator PUF is presented.

27 August 2020 in IEEE Access
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Journal Article
Open access
MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
GDGuillermo Díez-Señorans
Guillermo Díez-Señorans
CSCarlos Sanchez-Azqueta
Carlos Sanchez-Azqueta
SCSantiago Celma
Santiago Celma
In this paper, the possibility of using Galois ring oscillators to construct physically unclonable functions (PUFs) has been studied. The idea is to use novel PUF architectures, similar as the ring oscillator PUFs that, instead of comparing frequencies, compare the statistical bias of pairs of oscillators implemented in different locations. To study the viability of these systems, three different Galois oscillators have been implemented in several locations in several FPGAs and we have studied the main properties of their bias: repeatability, variability with the location, variability with the FPGA and spatial autocorrelation. Based on this study, we have determined that the bias of these oscillators meet the requirements that are needed to be used to construct a PUF. Finally, a PUF based on comparing the bias of neighboring 7-LUT Galois ring oscillators have been implemented and analyzed. The experimental results show that this PUF generates uniform responses that are highly reproducible and unique, making this PUF suitable for being used in identification applications.

21 June 2018 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
APAdrián Pérez
Adrián Pérez
MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
CSCarlos Sanchez-Azqueta
Carlos Sanchez-Azqueta
SCSantiago Celma
Santiago Celma
Industrial Ethernet is a technology widely spread in factory floors and critical infrastructures where a high amount of data need to be collected and transported. Fiber optic networks at gigabit rates fit well with that type of environment, where speed, system performance, and reliability are critical. In this paper, a new encryption method for high-speed optical communications suitable for such kinds of networks is proposed. This new encryption method consists of a symmetric streaming encryption of the 8b/10b data flow at physical coding sublayer level. It is carried out thanks to a format preserving encryption block cipher working in CTR (counter) mode. The overall system has been simulated and implemented in a field programmable gate array. Thanks to experimental results, it can be concluded that it is possible to cipher traffic at this physical level in a secure way. In addition, no overhead is introduced during encryption, getting minimum latency and maximum throughput.

26 September 2018 in IEEE Transactions on Circuits and Systems I: Regular Papers
Verified
Journal Article
Closed access
APAdrián Pérez
Adrián Pérez
MGMiguel Garcia-Bosque
Miguel Garcia-Bosque
CSCarlos Sanchez-Azqueta
Carlos Sanchez-Azqueta
SCSantiago Celma
Santiago Celma
In this paper, a new physical layer encryption method for optical 10-Gb Ethernet links is proposed. Necessary modifications to introduce encryption in Ethernet 10GBase-R standard have been considered. This security enhancement has consisted of a symmetric streaming encryption of the 64b/66b data flow at physical coding sublayer level thanks to two keystream generators based on a chaotic algorithm. The overall system has been implemented and tested in a field programmable gate array. Ethernet traffic has been encrypted, transmitted, and decrypted over a multimode optical link. Experimental results are analyzed concluding that it is possible to cipher traffic at this level and hide the complete Ethernet traffic pattern from any passive eavesdropper. In addition, no overhead is introduced during encryption, getting no losses in the total throughput.