This paper present Static Random Access Memory (SRAM) cell with minimum number of transistor. A conventional SRAM cell requires 6 transistors having two nodes contains normal and complimented data. The scaling of CMOS technology has significant impacts on working of SRAM cell. In 4T cell reading and writing has been performed by each node separately [1]. In this paper SRAM cell (2T) designed and comparison between them made in terms of power consumed, access time and PDP. A 2T cell contains single node, read and write performed through same node. It is found that in 2T cell area reduces by more than 66% maintaining same access time but at the cost of power consumption.

This paper thoroughly analyses all major ATPG (Automatic Test Pattern Generator) techniques to predict which of these would be optimal for a specific bit sized CUT (Circuit Under Test) when incorporated with BIST (Built-in-Self-Test). ISCAS benchmark circuits (74XX series) were used as CUT's and LFSR (Linear Feedback Shift Register), BS-CSFR (Bit-Swapping Complete Feedback Shift Register) and CA (Cellular Automata) based prominent ATPG techniques were used as vector generators. To make the predictions stronger, simulation was carried out on two benchmark circuits by Texas Instruments IC number 74181 and 74283. LFSR is the fundamental pattern generator and will serve as the base of comparison. BS-CFSR has shown promising transition density reduction without affecting the pseudo-randomness in the patterns whereby reducing the power considerably. CA avoids long feedback loops and communicates with neighbour cells only, which in turn helps to generate more random patterns and have better fault coverage. Xilinx ISE 14.7 and Cadence Encounter RTL Compiler RC 14.10 for coding in Verilog and implementation were used for timing responses, power consumption, delay and area of each implementation at 45 nm technology node.

The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell’s operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions.