An embedded system for gamma and neutron discrimination in mixed radiation environments is proposed, validated with an off-the-shelf detector consisting of a Cs2LiYCl6:Ce (CLYC) crystal coupled to a silicon photomultiplier (SiPM) cell array. This solution employs a machine learning classification model based on a multilayer perceptron (MLP) running on a commercial Field-Programmable Gate Array (FPGA), providing online single-event identification with 98.2% overall accuracy at rates higher than 200 kilocounts per second. Thermal neutrons and fast neutrons up to 5 MeV can be detected and discriminated from gamma events, even under pile-up scenarios with a dead-time lower than 2.5 μs. The system exhibits excellent size, weight, and power consumption (SWaP) characteristics, packed in a volume smaller than 0.6 liters and weighing less than 0.5 kilograms, while ensuring continuous operation with only 1.5 Watt. These features render our proposal suitable for embedded applications where low SWaP is critical and radiation levels manifest large count rate variability, such as space exploration, portable dosimeters, radiation surveillance on uncrewed aerial vehicles (UAV), and soil moisture monitoring.

A simplified correlation index is proposed to be used in real-time pulse shape recognition systems. This index is similar to the classic Pearson’s correlation coefficient, but it can be efficiently implemented in FPGA devices with far fewer logic resources and excellent performance. Numerical simulations with synthetic data and comparisons with the Pearson’s correlation show the suitability of the proposed index in applications such as the discrimination and counting of pulses with a predefined shape. Superior performance is evident in signal-to-noise ratio scenarios close to unity. FPGA implementation of Person’s method and the proposed correlation index have been successfully tested and the main results are summarized.

Machine learning models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high computational complexity. Due to their parallel processing capabilities, reconfigurability, and low power consumption, Systems on Chip based on a Field Programmable Gate Array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a Deep Neural Network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This paper presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization with an ensemble of compression techniques.