We explore optical switching to extend network programmability to the physical layer and discuss applications of a Layer-1 software-defined network (SDN) in AI/HPC clusters. In this context we identify two applications for optical circuit switches (OCSs): failure resilience and reconfigurable topologies for deep learning workloads. We present experimental results from a DGX-based testbed towards improving failure resilience and a simulation analysis for efficient deep learning training in AI clusters.

This paper presents an experimental performance characterization of all-optical subsystems at 40 Gb/s using interconnected hybrid integrated all-optical semiconductor optical amplifier (SOA) Mach-Zehnder interferometer (MZI) gates and flip-flop prototypes. It was shown that optical gates can be treated as generic switching elements and, when efficiently interconnected, can form larger and more functional network subsystems. Specifically, this paper reports on all-optical subsystems capable of performing on-the-fly packet clock recovery, 3R regeneration, label/payload separation, and packet routing using the wavelength domain. The all-optical subsystems are capable of operating with packet-mode traffic and are suitable for all-optical label-switched and self-routed network nodes. The intelligent functionality offered, combined with the compactness and stability of the optical gates, verifies the potential that all-optical technology can find application in future data-centric networks with efficient and dynamic bandwidth utilization. This paper also reports on the latest photonic integration breakthroughs as a potential migration path for reducing fabrication cost by developing photonic systems-on-chip utilizing multiple SOA-MZI optical gates on a single chip

The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical latching element that comprises an integrated semiconductor optical amplifier and Mach-Zehnder inteferometer and a feedback loop. Experimental proof-of-concept verification is presented at 8 Mb/s using off-the-shelf bulk components and a fiber-based feedback implementation. The proposed TFF architecture requires the minimum number of active components and just a single toggling signal as input. Its simple circuit design is amenable with photonic integration and holds the credentials for operation at multi-Gb/s speeds.

Conventional 850 nm multimode fiber links deployed in warehouse-scale data centers will be limited by modal dispersion beyond 10 Gb/s when covering distances up to 1 km. This can be resolved by opting for a single-mode fiber (SMF), but typically requires the use of power-hungry edge-emitting lasers. We investigate the feasibility of a high-efficiency SMF link by reporting a 0.13 μm SiGe BiCMOS laser diode driver optimized for long-wavelength vertical-cavity surface-emitting lasers (VCSELs). Bit-error rate experiments at 28 and 40 Gb/s up to 1 km of SMF reveal that four-level pulse amplitude modulation can compete with non-return-to-zero in terms of energy efficiency and scalability. With 9.4 pJ/b, the presented transmitter paves the way for VCSEL-based SMF links in data centers.

We present recent advances in photonic integration introduced by integration-related European research project IST-MUFINS. The contribution of the project in the progress of a functional photonic integration is outlined, from device fabrication to device application focusing on photonic routing using multielement photonic chips. Specifically, we report on the transition from single-element to multielement photonic devices with the fabrication of hybrid integrated arrays of optical switches exploiting and upgrading the silica-on-silicon hybrid photonic integration. We demonstrate how the enhanced processing power and capacity of these components can be exploited to implement key functionalities required in next-generation fully integrated terabits per second photonic routers.