This paper presents a low-power CMOS transconductance “gm” boosted common gate (CG) ultrawideband (UWB) low noise amplifier (LNA) architecture, operating in the 3-5 GHz range, employing current-reuse technique. This proposed UWB CG LNA utilizes a common source (CS) amplifier as the gm-boosting stage which shares the bias current with the CG amplifying stage. A detailed mathematical analysis of the LNA is carried out and the different design tradeoffs are analyzed. The LNA circuit was designed and fabricated using the 130-nm IBM CMOS process and it achieved input return loss (S₁₁) and output return loss (S₂₂) variations of respectively - 8.4 to - 40 dB and - 14 to - 15 dB within the pass-band. The LNA exhibits almost flat forward power gain (S₂₁) of 13 dB and a reverse isolation (S₁₂) variation of -55 dB to -40 dB, along with a noise figure (NF) ranging between 3.5 and 4.5 dB. The complete circuit (with output buffer) draws only 3.4 mW from a 1 V supply voltage.

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations.

A CMOS low-noise preamplifier for application in a 3.1-10.6-GHz ultrawideband radio-frequency (RF) receiver system is presented. This is essentially a wideband-pass multistage RF preamplifier using a cascade of a three-segment band-pass LC ¿ -section filter with a common-gate stage as the front end. Fundamental design analysis in terms of gain, bandwidth, noise, and impedance matching for the amplifier is presented in detail. The preamplifier was fabricated using the low-cost TSMC 0.18-¿m 6M1P CMOS process technology. The amplifier delivered a buffered power gain (S ₂₁) of ¿ 14 dB with a -3-dB bandwidth (between the corner frequencies) of around 7.5 GHz. It consumed around 30 mW from a 2.5-V supply voltage. It had a minimum passband noise figure of around 4.7 dB, an input-referred third-order intercept point of -5.3 dBm, and reverse isolation (S ₁₂) under -65 dB.

An optimized 866 MHz CMOS LNA for UHF radio-frequency identification reader is presented. It achieves simultaneous impedance and minimum F _min noise matching at a very low-power drain of 850 μW from a 0.7-V supply voltage. Compared to other GHz LNA designs, this UHF LNA design using sub-1 V supply voltage is quite challenging due to the inductor size and bias drain-related noise factor degradation. The LNA was fabricated using the 130-nm IBM CMOS process. Compared to previously reported narrow-band LNA designs, inclusion of the finite g _ds effect is found to improve the nanometric design optimization. The low-cost packaged LNA was tested using external lumped element and microstrip line matching. The LNA delivered a power gain ( S ₂₁ ) of ≈17 dB and an input power reflection (S11 @ 866 MHz) of ≈ -30 dB. It had a minimum pass-band noise figure of around 2.2 dB and a third-order input-referred intercept point of ≈ -11.5 dBm.

A low-power noise-matched fully-differential common-gate (CG) low-noise amplifier (LNA) is presented for ultra-wideband (UWB) operating in the 3.1–10.6 GHz band. Performance was optimised by employing the transconductance ‘g_m’-boosted CG LNA topology with series peaking along with an input noise matching network. A common source g_m-boosting amplifier, in conjunction with an LC T-network, was used to share the bias current with the CG stage. The LNA was demonstrated using 130 nm CMOS process and consumed 7 mW from a 1 V supply. It exhibited an input return loss (S₁₁) and an output return loss (S₂₂) of −10.5 dB and −14 dB, respectively. Also, it achieved a forward power gain (S₂₁) of 14.5 dB and a noise figure between 4.5 and 5.0 dB.