LEI ZHANG

Ms. LEI ZHANG


Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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16 June 2022 in Electronics
Verified
Journal Article
Open access
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Yuxuan XingYuxuan Xing
Yuxuan Xing
LZLEI ZHANG
LEI ZHANG
ZHZhixian Hou
Zhixian Hou
Xiaoran LiXiaoran Li
Xiaoran Li
YSYueting Shi
Yueting Shi
LYLiang Yan
Liang Yan
Electrocardiogram (ECG) heartbeat classification plays a vital role in early diagnosis and effective treatment, which provide opportunities for earlier prevention and intervention. In an effort to continuously monitor and detect abnormalities in patients’ ECG signals on portable devices, this paper present a lightweight ECG heartbeat classification method based on a spiking neural network (SNN), a relatively shallow SNN model integrated with a channel-wise attentional module. We further explore the best-optimized architecture, which benefits from leveraging the full advantages of the SNN potential with the attention mechanism to process the classification task at low power and capture prominent features concerning the time, morphology, and multi-channel representations of the ECG signal. Results show that our model achieves overall classification accuracy of 98.26%, sensitivity of 94.75%, and F1 score of 89.09% on the MIT-BIH database, with energy consumption of 346.33 μJ per beat and runtime of 1.37 ms. Moreover, we have conducted multiple experiments to compare against current state-of-the-art methods using their assessment strategies to evaluate our model implementation on FPGA. So far, our work achieves comparable overall performance with all the literature in terms of classification accuracy, energy consumption, and real-time capability.

1 August 2018 in Sensors
Verified
Journal Article
Open access
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LZLEI ZHANG
LEI ZHANG
SRShiwei Ren
Shiwei Ren
XLXiangnan Li
Xiangnan Li
GRGuishan Ren
Guishan Ren
XWXiaohua Wang
Xiaohua Wang
In this paper, a generalized L-shaped nested array based on the fourth-order difference co-array is proposed for two-dimensional (2D) directions’ estimation. The new structure framework makes full use of the physical sensor locations to form a virtual uniform rectangular array (URA) as large as possible. As it utilizes the fourth-order difference instead of the traditional second-order difference result, this structure framework can acquire a much higher degree-of-freedom (DOF) than the existing 2D sparse arrays. The proposed structures have two advantages. One is that the subarrays can be chosen as any nested-class arrays, which makes the sparse array design more flexible. We can choose arbitrary subarray structures for DOF enhancement purposes. Another advantage is that the relative position of two subarrays can be set as any integral multiple of half wavelength. This means that two subarrays can be located as far as possible so that the relative influence between two physical subarrays can be ignored. The DOFs of several typical generalized L-shaped nested arrays (GLNAs) are compared in this paper. By setting the subarrays as different types and the relative position as a special value, a special GLNA is presented. Simulations show that GLNAs have obvious superiority in 2D direction-of-arrival estimation.

9 November 2022 in Electronics
Verified
Journal Article
Open access
PDF file
LKLiu Kun
Liu Kun
YXYaoming Xie
Yaoming Xie
Xiaoran LiXiaoran Li
Xiaoran Li
LZLEI ZHANG
LEI ZHANG
A low-dropout linear regulator (LDO) without external capacitors is designed, combining ultra-low power consumption and ultra-fast transient response. The common support voltage of the LDO is 2.5 V to 3.6 V with a stable output voltage of 1.2 V and an output current dynamic range of 10 μA to 20 mA to supply power to other circuit modules. A Rail-to-Rail Input-Output (RRIO) Class AB push-pull output amplifier and a dynamic bias circuit are also designed. Meanwhile, a dynamic bias circuit which can regulate the operating current of error amplifier is proposed by monitoring output voltage variation in order to provide a larger compensation current to the operational amplifier when the load current changes are at high frequency and maintain ultra-low operating current at low clock frequency. The LDO is designed without resistors, and the deep well NMOS is applied in the output stage in order to reduce the difficulty of loop compensation. Designed in a 180 nm CMOS process, the post-simulation results show that under the condition of 40 °C and 3 V input voltage, the static power consumption is 31.7 nA with a settling time (±5%) of less than 35 ns.

30 June 2023
Verified
Book Chapter
Open access
PDF file
ZWZhenxing Wu
Zhenxing Wu
LZLEI ZHANG
LEI ZHANG
WYWeihua Yu
Weihua Yu
XWXinghua Wang
Xinghua Wang
Xiaoran LiXiaoran Li
Xiaoran Li
This paper explores the teaching mode in digitalization and informatization, taking integrated circuit major as an example. By introducing practical engineering projects into curriculum practice and taking discipline competitions as the guide, it is explored new method to improve the ability to solve complex problems. It is built a self-circulating, self-iteration, scientific and technological innovation platform for students, building online and offline mode by cloud service to meet their requirements. After years of practice, this method can effectively stimulate students' internal driving force, improve their comprehensive qualities such as knowledge mastery, professional practice and application ability. It is proved that this way is effective to cultivate high-quality compound new engineering talents with strong practical ability, strong innovation ability and international competitiveness.