Photonics-based neural networks promise to outperform electronic counterparts, accelerating neural network computations while reducing power consumption and footprint. However, these solutions suffer from physical layer constraints arising from the underlying analog photonic hardware, impacting the resolution of computations (in terms of effective number of bits), requiring the use of positive-valued inputs, and imposing limitations in the fan-in and in the size of convolutional kernels. To abstract these constraints, in this paper we introduce the concept of Photonic-Aware Neural Network (PANN) architectures, i.e., deep neural network models aware of the photonic hardware constraints. Then, we devise PANN training schemes resorting to quantization strategies aimed to obtain the required neural network parameters in the fixed-point domain, compliant with the limited resolution of the underlying hardware. We finally carry out extensive simulations exploiting PANNs in image classification tasks on well-known datasets (MNIST, Fashion-MNIST, and Cifar-10) with varying bitwidths (i.e., 2, 4, and 6 bits). We consider two kernel sizes and two pooling schemes for each PANN model, exploiting $$2\times 2$$2 × 2 and $$3\times 3$$3 × 3 convolutional kernels, and max and average pooling, the latter more amenable to an optical implementation. $$3\times 3$$3 × 3 kernels perform better than $$2\times 2$$2 × 2 counterparts, while max and average pooling provide comparable results, with the latter performing better on MNIST and Cifar-10. The accuracy degradation due to the photonic hardware constraints is quite limited, especially on MNIST and Fashion-MNIST, demonstrating the feasibility of PANN approaches on computer vision tasks.

Forthcoming 6G/NextG networks highlight the need for advanced Artificial Intelligence (AI)-based security mechanisms to identify malicious activities and adapt to emerging threats. In this context, the integration of computer vision techniques into the cybersecurity field is promising due to their potential for sophisticated pattern recognition. In this paper we introduce a computationally efficient classification scheme acting directly on the raw packets collected at base stations and enforcing real-time conversion of packets into images. The innovative points of the proposed solution are the lightweight implementation, aligning well with the demands of future 6G networks, and the operation at network edge, enabling early threat identification as close as possible to the packet origin. We investigate the performance of this approach both in terms of F1-score and prediction time using state-of-the-art computer vision architectures and a customized Convolutional Neural Network (CNN) in an intrusion detection problem using a 5G dataset. Experimental results show the superiority of the CNN architecture over complex models. Across multiple packet window sizes N (i.e., 10, 50, 100 packets), the CNN consistently outperforms the other state-of-the-art computer vision models, achieving very high F1-scores (namely, 0.99593, 0.99860, 0.99895). A scalability analysis highlights a trade-off between CNN scalability and performance, where larger N values lead to increased prediction time. On the other hand, the other computer vision models exhibit better scalability, enabling an optimal model selection without trade-offs.

The Open Computing Language (OpenCL) is increasingly adopted for programming processors with reconfigurable hardware acceleration. The 5G telecommunication infrastructure, imposing strong latency constraints on the managed communications, may benefit from OpenCL-designed accelerated processing. This paper presents the first study to evaluate OpenCL hardware acceleration in the context of a 5G base station physical layer. The implementation and optimization process to accelerate the Orthogonal Frequency Division Multiplexing (OFDM) part of the 5G downlink is conducted on a high-end Field Programmable Gate Array (FPGA). We show that the proposed OpenCL implementation complies with the 5G processing timing requirements since the computation time is consistent with the present 5G deployment. However, to be suitable for 5G, the OpenCL platform must improve the data latency transfer between hardware and software. Moreover, a further enhancement for the OpenCL implementation is to improve the code by means of OpenCL optimization techniques. In this way, the performance can be further improved with respect to optimized software on vectorized high-end processors.

Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In such a scenario, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely support the possibility of updating the application parameters and changing the running computer vision applications at run-time. In this respect, this paper presents a novel SCN node architecture based on a device in which a microcontroller manages all the network functionality as well as the remote configuration, while an FPGA implements all the necessary module of a full computer vision pipeline. In the paper the envisioned architecture is first detailed in general terms, then a real implementation is presented to show the feasibility and the benefits of the proposed solution. Finally, performance evaluation results prove the potential of hardware software codesign in reaching flexibility and reduced latency time.

The design and development of distributed innovative services leveraging pervasive smart camera network solutions requires the use of reconfigurable low-cost smart cameras. In this respect, FPGA based Smart Cameras enabled to wireless communication that follow the Internet of things paradigm are a promising solution. The paper proposes an optimized design of the histogram extractor algorithm targeted to low-complexity and low-cost FPGA based Smart Cameras. The proposed solution is the basis for a wide range of distributed computer vision applications. We first define a general architecture for the image histogram core, then we evaluate its performance with a real implementation.