Dr. Yanjie Wang

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Academic Career Length

13Years (2014-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

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12 January 2024 in IEEE Journal of Solid-State Circuits

Journal Article

A 52–73-GHz LNA With Tri-Coupled Transformer for G _m Boosting and Enhanced Noise Canceling

Jiacong Ke

Zetian Lin

Guangyin Feng

Yanjie Wang

This article presents a broadband low-noise amplifier (LNA) based on tri-coupled transformer (XFMR) for ${G}_{m}$ boosting and enhanced noise canceling (NC). In contrast to conventional NC structures, the proposed design uses the combination of a single transistor and a tri-coupled XFMR innovatively to achieve noise reduction, ${G}_{m}$ boosting, as well as wideband matching, simultaneously. Fabricated in a 40-nm CMOS process, the LNA achieves a 3-dB bandwidth of 22.1 GHz from 51.6 to 73.7 GHz, a peak gain of 22.4 dB, a minimum NF of 3.8 dB, and an average IP1dB of −12 dBm with a dc power consumption of 34 mW.

3 March 2016 in IEEE Transactions on Microwave Theory and Techniques

Journal Article

An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration

Charles Wu

Yanjie Wang

Borivoje Nikolic

Christopher Hull

A mixer-first receiver design in 28-nm CMOS is discussed. An embedded 5-bit mixer digital-to-analog converter provides wideband tuneability to enhance device matching and, hence, suppress the multiple local oscillator (LO) harmonics as well as to improve the overall image rejection (IR) performance. Two-stage baseband amplifiers support a 50-MHz baseband bandwidth, which covers the entire channel for long-term evolution non-contiguous carrier aggregation. The proposed design effectively reduce multiple LO harmonics down to below -62 dBm. The system achieves 2.6-dB noise figure, > 15-dBm out-of-band third-order input intercept point, and an IR ratio > 66 dB with 60-mW power, including five on-chip low dropout regulators.

17 March 2021 in IEEE Journal of Solid-State Circuits

Journal Article

A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm P_sat and 26.5% PAE in 16-nm FinFET CMOS

Kun-Da Chu

Steven Callender

Yanjie Wang

Jacques Christophe Rudell

Stefano Pellerano

Christopher Hull

This article presents the design of a dual-mode V-band power amplifier (PA) that enhances the efficiency at power back-off (PBO) using load modulation. The PA utilizes a reconfigurable two-/four-way power combiner to enable two discrete modes of operation-full power and back-off power. The power combiner employs two techniques to further improve the PA efficiency at PBO: 1) usage of transformers with non-uniform turns ratios to reduce the difference in impedance presented to the PA cores between the two modes and 2) utilize a proposed switching scheme to eliminate the leakage inductance associated with the disabled path in back-off power mode (BPM). The two-stage PA achieves a peak gain of 21.4 dB with a fractional BW (fBW) of 22.6% (51-64 GHz). At 65 GHz, the PA has a Psat of +17.9 dBm with an OP1,dB of +13.5 dBm and a peak power added efficiency (PAE) of 26.5% in full-power mode. In BPM, the measured Psat, OP1,dB, and peak PAE are +13.8 dBm, +9.6 dBm, and 18.4%, respectively. The PAE is enhanced by 6% points at a 4.5-dB back-off. The PA is capable of amplifying a 6 Gb/s 16-QAM modulated signal with an EVMrms of -20.7 dB at an average Pout/PAE of +13 dBm/13.6%, respectively. This PA was implemented in 16-nm FinFET, occupies a core area of 0.107 mm², and operates under a 0.95-V supply.

9 April 2024 in Microelectronics Journal

Journal Article

A 6-/12-dB back-off reconfigurable Doherty-like load modulated balanced amplifier with compact area and wide bandwidth

Xianfeng Que

Yanjie Wang

Shangyao Huang

12 May 2024 in Electronics

Journal Article

A High-Gain Metallic-via-Loaded Antipodal Vivaldi Antenna for Millimeter-Wave Application

This paper presents a miniaturized-structure high-gain antipodal Vivaldi antenna (AVA) operating in the millimeter-wave (mm-wave) band. A gradient-length microstrip-patch-based director is utilized on the flares of the AVA to enhance gain. Additionally, an array of metallic vias is incorporated along the lateral and horizontal edges of the antenna for further gain enhancement and bandwidth extension. Based on the proposed structure, the AVA can achieve a peak gain of 11.9 dBi over a relative bandwidth of 71.24% within 16.5–36.6 GHz as measured, while the electrical dimension is only 1.54 × 2.69 × 0.07

{λ_{c}}^{3}

. The measured results show good agreement with the simulated ones. Owning the characteristics of being high-gain and ultra-wideband, and having a compact size, the proposed AVA can be a competitive candidate for future millimeter-wave communication.

11 May 2024 in Electronics

Journal Article

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

Xianfeng Que

Jun Li

Yanjie Wang

This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (

P_{sat}

) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (

P_{avg}

) and 47–53% average drain efficiency (

{DE}_{avg}

). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD).

About Me

Yanjie Wang (Senior Member, IEEE) received an M.A.Sc. degree from Carleton University, Ottawa, ON, Canada, in 2002, and a Ph.D. degree from the University of Alberta, Edmonton, AB, Canada, in 2009. He was an ASIC Design Engineer with Nortel Networks, Montreal, QC, Canada, and AMCC, Ottawa, ON, from 1999 to 2003. In 2007, he joined the Berkeley Wireless Research Center, University of California at Berkeley, Berkeley, CA, USA, as a Ph.D. Research Scholar. He has been with Intel Corporation, Hillsboro, OR, USA, since 2008, where he was as a Senior Staff Research Scientist, with a research focus on 5G mmW and energy-efficient broadband RF transceiver circuits and systems. He is currently a Full Professor and the Associate Dean of the Microelectronics School, South China University of Technology, Guangzhou, China. Dr. Wang served as a TPC Member for the IEEE RFIC and has been an Organization Committee Member for the IEEE CICC, since 2012. He was a co-recipient of the Lewis Winner Award Outstanding Paper and Industrial Recognition Award at ISSCC2020, the Best Invited Paper Award of the IEEE CICC2017, the Best Paper Award (Second Place) of the IEEE CICC2017, the Best Paper Final List of the IEEE RFIC 2008, the Queen Elizabeth II Doctoral Scholarship from 2006 to 2009, the Doctoral Entree Award in 2005, and the Faculty of Graduate Study Research Abroad Award in 2007 at the University of Alberta.

Dr. Yanjie Wang

Dr. Yanjie Wang

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About Me