This paper presents a wideband common-gate (CG) LNA architecture that overcomes the fundamental tradeoff between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure (NF) over the previously reported feedback amplifiers in a CG configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. An amplifier prototype was realized in 0.18-μm CMOS, operates from 1.05 to 3.05 GHz, and dissipates 12.6 mW from 1.8-V supply while occupying a 0.073-mm² active area. The LNA provides 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than - 10-dB input matching, and - 0.7-dBm minimum IIP₃ across the entire bandwidth.

In this paper, a CMOS on-chip sensor is presented to detect dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of an LC voltage-controlled oscillator (VCO) upon the change of the tank capacitance when exposed to the liquid. To make the system self-sustained, the VCO is embedded inside a frequency synthesizer to convert the frequency shift into voltage that can be digitized using an on-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. The dielectric constants of different organic liquids have been detected in the frequency range of 7-9 GHz with an accuracy of 3.7% compared with theoretical values for sample volumes of 10-20 μL. The sensor is also applicable for binary mixture detection and estimation of the fractional volume of the constituting materials with an accuracy of 1%-2%.

A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm ² with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

A wideband inductorless low-noise-amplifier (LNA) with single-to-differential conversion for multistandard radio applications is proposed. Noise-suppressed current-mirror-based biasing is utilized to ensure stable operation under process, voltage, and temperature variations. The inherent gain of the common-source (CS) stage is re-used to boost the trans-conductance of the common-gate (CG) stage, and hence, a noise- and power-efficient design is achieved without hurting the noise and distortion cancellation properties of the CG-CS-based balun topology. The gain and phase balance is improved by employing an efficient compensation scheme. The prototype was realized in 0.13- μm CMOS, operates from 0.1 to 2 GHz, and dissipates 3 mW from 1.2-V supply while occupying a 0.075-mm² active area. The balun-LNA, including the output buffer, provides 7.6-dB maximum power gain, 4.15-dB minimum noise figure, better than -10-dB input matching, and 0.5-dBm IIP₃ without any on-chip inductor.

A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10^-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.

A highly linear I-channel receiver prototype is presented for a 3-6-GHz broadband radio system with a 200-MHz baseband bandwidth and verified to operate under congested spectrum environments. A direct conversion receiver developed from this prototype is suitable for a cognitive radio, a fifth-generation (5G) receiver, and other wireless systems with a total (in-band signal plus blocker) power of above -6.0 dBm. The broadband receiver consists of a low-noise transconductance amplifier (LNTA), a passive mixer, a wideband transimpedance amplifier, and a power-efficient minimally invasive baseband filter. The LNTA with high linearity employs a cross-coupled structure and resistive degeneration to achieve low noise and high linearity simultaneously. The common-gate-based LNTA achieves 2.3-dB noise figure in simulation. Fabricated in a mainstream 40-nm CMOS technology, the worst case measured system noise figure is under 5.8 dB at 3-MHz baseband frequency, and the conversion gain is larger than 12.8 dB with passband variations under 2 dB from 1- up to 200-MHz signal bandwidth. Over 3-6 GHz, the receiver's in-band input third-order intercept point (IIP3) and input P1db are higher than 15.1 and 3.0 dBm, respectively, whereas the power consumption varies from 64.1 to 69.6 mW.