The high operating voltage and switching speed of silicon carbide (SiC) MOSFETs have significant impacts on parasitic elements. This leads to a limitation in the performance of the devices. Especially in the bridge-leg configuration, the coupling of the parasitic elements, in the upper and lower bridge-legs, produces knock-on effects, which complicates the modeling development to reveal the underlying mechanisms. This paper presents a detailed piecewise linear analytical model for bridge-leg configured SiC MOSFETs, which takes into account their characteristics and all parasitic elements. The novelty of the proposed model lies in the fact that the critical parameters in each stage are distinguished flexibly and emphatically according to their influence weights to the corresponding main variables. Therefore, the complexity of the model which considers all parasitic elements is reduced but the critical impacts on the switching processes are carefully kept. The turn-on and turn-off processes are analyzed stage-by-stage in detail with the derived critical parameters equivalent circuits, and the mechanism underlying how each critical parameter influences the model is revealed individually. Furthermore, based on this model, the impact mechanisms and trends of the switching rate variation, the power loop attenuation oscillation, and the driver loop crosstalk phenomenon for different critical parameters are analyzed emphatically. Double pulse measurements with a 600 V/20A SiC MOSFETs based bridge-leg test circuit are used for the experimental verification of the accuracy of the model and the trends of the critical parameters' impacts.

The dual-active-bridge (DAB) converter has emerged as a promising topology for renewable energy applications and microgrid systems due to its high power density and bidirectional energy-transfer capability. Enhancing the overall efficiency and reliability of DAB converters requires the simultaneous realization of zero-voltage switching (ZVS) across all switches and the minimization of current stress over wide load and voltage ranges—two objectives that are often in conflict. Conventional modulation strategies with limited degrees of freedom fail to meet these dual goals effectively. To address this challenge, this paper introduces an enhanced integrated optimization strategy based on triple phase shift (EIOS-TPS). This approach formulates the power transmission requirement as an equality constraint and incorporates ZVS and mode boundary conditions as inequalities, resulting in a comprehensive optimization framework. Optimal phase-shift parameters are obtained using the Karush–Kuhn–Tucker (KKT) conditions. To mitigate zero-current switching (ZCS) under a light load and achieve full-range ZVS with reduced current stress, a modulation factor λ is introduced, enabling a globally optimized control trajectory. An experimental 1176 W prototype is developed to validate the proposed method, which achieves full-range ZVS while maintaining low current stress. In the low-power region, it improves efficiency by up to 2.2% in buck mode and 2.0% in boost mode compared with traditional control strategies, reaching a peak efficiency of 96.5%.

The instantaneous output power of a two-stage single-phase inverter pulsates at twice the output voltage frequency (2f_o), which results in a large amount of second harmonic current (SHC) in the front-end dc–dc converter. This article proposes a novel dual-loop control strategy based on the parallel output impedance model of the front-end dc–dc converter, in order to reduce the SHC and improve the dynamic performance. The proportional–integral–resonant controller (PIRC) is used in the current-loop, and the SHC can be further suppressed under the limited loop bandwidth condition. In the voltage-loop, a notch filter is inserted into the forward path of the active disturbance rejection controller (ADRC). It allows the voltage-loop cutoff frequency to become greater than 2f_o, which significantly improves the load transient response. Furthermore, a step-by-step closed-loop parameters design method considering the SHC reduction, phase margin, and dynamic performance is proposed. Finally, a 1.8 kW two-stage single-phase inverter prototype is built and tested. The experimental results demonstrate the high effectiveness of the proposed dual-loop control strategy.