Nicolas Sklavos

Prof. Dr. Nicolas Sklavos

Associate Professor, SCYTALE Group, Computer Engineering and Informatics Department, University of Patras, Greece
orcid

Research Focus & Metrics

Academic Career Length

27Years (2000-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
1 March 2011 in Computers and Electrical Engineering
Verified
Journal Article
Closed access
Rodrigo Román-CastroRodrigo Román-Castro
Rodrigo Román-Castro
Crisitna AlcarazCrisitna Alcaraz
Crisitna Alcaraz
Javier LopezJavier Lopez
Javier Lopez
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos

1 June 2021 in Internet of Things
Verified
Journal Article
Closed access
SZSherali Zeadally
Sherali Zeadally
ADAshok Kumar Das
Ashok Kumar Das
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos

22 October 2012 in IEEE Security & Privacy
Verified
Journal Article
Closed access
Anastasios BikosAnastasios Bikos
Anastasios Bikos
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos
The authors give an overview on the state of the art of potential security issues that occur in the deployment of the LTE/SAE (Long-Term Evolution/System Architecture Evolution) protocol in emerging 4G wireless technologies. Although security concerns and challenges in wireless networks will remain a hot topic in the future, the LTE/SAE standard could adapt to these rising challenges, becoming more robust and secure. By looking at the authentication and ciphering algorithms, such as EAP-AKA (Extensible Authentication Protocol for Authentication and Key Agreement), currently operating within the LTE protocol, the authors analyze several vulnerabilities in LTE/SAE security architecture - specifically, insecure AKA key derivation procedures and the lack of fast reauthentications during handovers.

1 December 2002 in IEEE Transactions on Computers
Verified
Journal Article
Closed access
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos
OKO. Koufopavlou
O. Koufopavlou
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.

1 March 2005 in The Journal of Supercomputing
Verified
Journal Article
Closed access
PDF file
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos
OKO. Koufopavlou
O. Koufopavlou

4 November 2003
Verified
Conference Paper
Closed access
Nicolas SklavosNicolas Sklavos
Nicolas Sklavos
OKO. Koufopavlou
O. Koufopavlou
Couple to the communications wired and unwired networks growth, is the increasing demand for strong secure data transmission. New cryptographic standards are developed, and new encryption algorithms are designed, in order to satisfy the special needs for security. SHA-2 is the newest powerful standard in the hash functions families. In this paper, a VLSI architecture for the SHA-2 family is proposed. For every hash function SHA-2 (256, 384, and 512) of this standard, a hardware implementation is presented. All the implementations are examined and compared in the supported security level and in the performance by using hardware terms. This work can substitute efficiently the previous SHA-1 standard implementations, in every integrity security scheme, with higher offered security level, and better performance. In addition, the proposed implementations could be applied alternatively in the integrations of digital signature algorithms, keyed-hash message authentication codes and in random numbers generators architectures.