As task preemption/relocation with acceptably low overheads become a reality in today's reconfigurable FPGAs, they are starting to show bright prospects as platforms for executing performance critical task sets while allowing high resource utilization. Many performance sensitive real-time systems including those in automotive and avionics systems, chemical reactors, etc., often execute a set of persistent periodic safety critical control tasks along with dynamic event driven aperiodic tasks. This work presents a co-scheduling framework for the combined execution of such periodic and aperiodic real-time tasks on fully and run-time partially reconfigurable platforms. Specifically, we present an admission control strategy and preemptive scheduling methodology for dynamic aperiodic tasks in the presence of a set of persistent periodic tasks such that aperiodic task rejections may be minimized, thus resulting in high resource utilization. We used the 2D slotted area model where the floor of the FPGA is assumed to be statically equipartitioned into a set of tiles in which any arbitrary task may be feasibly mapped. The experimental results reveal that the proposed scheduling strategies are able to achieve high resource utilization with low task rejection rates over various simulation scenarios.

There is an increasing desire to conduct autonomous inspection of nuclear sites using robots. However, the presence of gamma radiation in nuclear sites induces degradation in vision sensors. In this paper, the effects of gamma radiation on a robot vision sensor (CMOS camera) used for radiological inspection is examined. The analyses have been carried out for two types of images at different dose rates: a) dark images b) illuminated images. In this work, dark images and chessboard images under illumination are analysed using various evaluation metrics to evaluate the effect of gamma radiation on CMOS Integrated Circuit (IC) and electronic circuitry of the sensor. Experimental results manifest significant changes in electrical properties like the generation of radiation-induced photo signal in sensing circuitry and radiation-induced noise affecting the visual odometry of the robot. System-level degradation for gamma dose rates upto 3 Gy/min intensifies, making data from the imaging sensor unreliable for the visual odometry. However, images captured for gamma dose rate upto 3 Gy/min can be used for surveillance purpose.

Field-programmable gate arrays (FPGAs) offer the flexibility of general-purpose processors along with the performance efficiency of dedicated hardware that essentially renders it as a platform of choice for modern-day robotic systems for achieving real-time performance. Such robotic systems when deployed in harsh environments often get plagued by faults due to extreme conditions. Consequently, the real-time applications running on FPGA become susceptible to errors which call for a reliability-aware task scheduling approach, the focus of this article. We attempt to address this challenge using a hybrid offline–online approach. Given a set of periodic real-time tasks that require to be executed, the offline component generates a feasible preemptive schedule with specific preemption points. At runtime, these preemption events are utilized for fault detection. Upon detecting any faulty execution at such distinct points, the reliability-aware scheduling approach, RASA, orchestrates the recovery mechanism to remediate the scenario without jeopardizing the predefined schedule. Effectiveness of the proposed strategy has been verified through simulation-based experiments and we observed that the RASA is able to achieve 72% of task acceptance rate even under 70% of system workloads with high fault occurrence rates.

Recent times are witnessing an emergence of sites that are hazardous for human access. This has created a global demand to equip agents with the ability to autonomously inspect such environments by computing a coverage path effectively and efficiently. However, inspection of such sites requires agents to consider the correlation of work, providing precedence provision in visiting regions. The current approaches to compute coverage path in the hazardous sites, however, do not consider precedence provision. To this end, coverage path planning strategies are proposed, which provide precedence provision. To meet the challenges, the problem is divided into two phases: inter-region and intra-region path planning. In the ‘inter-region’ path planning of the approach, the site comprising of multiple disjoint regions is modelled as connectivity graph. Two novel approaches, Mixed Integer Linear Programming (MILP) solution and heuristic based techniques, are proposed to generate the ordered sequence of regions to be traversed. In the ‘intra-region’ path planning of the approach, each region is decomposed into a grid and Boustrophedon Motion is planned over each region. The ability of combined approach to provide complete coverage is proved under minor assumption. An investigative study has been conducted to elucidate the efficiency of the proposed approach in different scenarios using simulation experiments. The proposed approach is evaluated against baseline approaches. The results manifest a significant reduction in cost and execution time, which caters to inspection of target sites comprising of multiple disjoint regions with precedence provision.

Enhancing result-accuracy in approximate computing (AC) based real-time systems, without violating power constraints of the underlying hardware, is a challenging problem. Execution of such AC real-time applications can be split into two parts: (i) the mandatory part , execution of which provides a result of acceptable quality, followed by (ii) the optional part , that can be executed partially or fully to refine the initially obtained result in order to increase the result-accuracy, without violating the time-constraint. This article introduces DELICIOUS , a novel hybrid offline-online scheduling strategy for AC real-time dependent tasks. By employing an efficient heuristic algorithm , DELICIOUS first generates a schedule for a task-set with an objective to maximize the results-accuracy, while respecting system-wide constraints. During execution, DELICIOUS then introduces a prudential cache resizing that reduces temperature of the adjacent cores, by generating thermal buffers at the turned off cache ways. DELICIOUS further trades off this thermal benefits by enhancing the processing speed of the cores for a stipulated duration, called V/F Spiking , without violating the power budget of the core, to shorten the execution length of the tasks. This reduced runtime is exploited either to enhance result-accuracy by dynamically adjusting the optional part, or to reduce temperature by enabling sleep mode at the cores. While surpassing the prior art, DELICIOUS offers 80% result-accuracy with its scheduling strategy, which is further enhanced by 8.3% in online, while reducing runtime peak temperature by 5.8°C on average, as shown by benchmark based evaluation on a 4-core based multicore.

Continuous demands for improved performance within constrained resource budgets are driving a move from homogeneous to heterogeneous processing platforms for the implementation of today’s Real-Time (RT) embedded systems. The applications executing on such systems are typically represented as a Precedence Task Graph (PTG), where a node represents a task or algorithm for one functionality and edges represent the complex interactions between multiple functionalities. Due to RT constraints, the task graph needs to be executed within a specified deadline. Although some existing studies have looked into solving this challenge, comprehensive studies that combine the theoretical features of RT task-graph mapping and scheduling with practical runtime architectural characteristics have mostly been ignored to date. Hence, in this article, we consider the challenge of scheduling an RT application modeled as a single PTG, with the objective of minimizing the overall execution time under Hardware (HW) resource and deadline constraints for heterogeneous Central Processing Unit (CPU) + Field Programmable Gate Array (FPGA) architectures. First, we introduce an optimal solution using Integer Linear Programming (ILP). However, this ILP-based optimal solution suffers from computational complexity and does not scale well even for moderately large problem sizes. Hence, we additionally propose heuristic algorithms for task mapping and scheduling. The efficiency of the proposed scheme, named MESSI, has been evaluated through experiments using PTG on a practical CPU+FPGA system regarding current technology restrictions. Our experiments demonstrate that performance gains of 55.6% and area usage reductions of 46.3% are possible compared to full Software (SW) and HW execution, respectively.