This paper presents a fault diagnosis method and system reconfiguration strategy of three level neutral-pointclamped cascaded inverter (3L-NPC-CI) to enhance reliability of power supply in electrified railway. First, neural network is employed to perform open-circuit fault diagnosis and identify fault switches. Then, system reconfiguration strategy is proposed to perform single phase 3L-NPC-CI reconfiguration. Through the analysis of the operation status of 3L-NPC, there are eight fault modes in single bridge arm, including single-switch fault and double-switches fault. By the feature analysis for the output arm voltage harmonic of normal and eight fault modes, seven harmonic parameters are selected as fault feature vectors. Meanwhile, a three-layer neural network is constructed, and the seven feature vectors are the input layer of the neural network. By training algorithm, the fault switches location can be identified accurately about one modulation period. Then, the fault module is bypassed and the 3L-NPC-CI system is stable by reconfiguring the modulation strategy of other normal modular. Simulation and experimental results are given to validate the proposed fault diagnosis and system reconfiguration strategy. The proposed method is able to improve robustness and reliability of 3L-NPCCI in traction power supply system.

An optimal active power filter (APF) based on modular multilevel converter (MMC) without load current and lower arm current sensors is proposed. Its control algorithm mainly includes predictive harmonic current control, fundamental frequency control, and dc voltage control. Comparing to direct current control, the first two subcontrollers transfer the harmonic and fundamental active/reactive power current to voltage references, which are suitable to generate the modulation signals to MMCs as well as two-level converters. Their full digital optimization structures combined with the MMC voltage and current control are detail discussed and implemented on field programmable gate array. The synthesis result indicates a low hardware resource utilization and calculation delay of the designed controller. The experimental results on an MMC-based APF prototype verified the static and dynamic performances of the proposed algorithm.

Voltage equalizer is essential for mitigating the inconsistencies of series-connected lithium-ion batteries in electric vehicles to ensure operation life and work safety. To keep voltage balancing, voltage equalizers are widely adopted in the battery string application. However, traditional voltage equalizers have high circuit costs and large sizes due to the need for a large number of MOSFETs and isolated gate drivers. Moreover, as the voltage difference between the batteries in the series decreases towards the end of the equalization process, the equalization current also decreases, which can affect the speed of voltage equalization. To overcome these problems, an isolated multiple half-bridge converter with a multiport transformer is proposed. The balancing circuit has two power transfer paths, allowing for energy transfer among multiple cells simultaneously, which could achieve a significant equalization current even when the voltage difference is close to zero. In the proposed equalizer, only one MOSFET is needed for one cell and two cells can share one transformer winding. Hence, it is more applicable for a large number of battery stacks, such as electric vehicles. Finally, to improve the equalization speed and efficiency, three equalization control strategies, i.e., average voltage, predicted voltage, and boundary voltage control strategies are introduced and verified by a 100 kHz 24-cell voltage equalization prototype.

The single-phase unified power quality conditioner (UPQC) is widely used to improve the power quality of sensitive end-users. However, the inherent instantaneous power difference between parallel and series converter will generate a significant low-frequency dc-link voltage ripple and degrade the compensation performance of UPQC. The generation mechanism of dc-link voltage ripple and its influences on compensation voltage and current are analyzed in this paper. To suppress the influence, a control strategy is proposed for the single-phase UPQC. For parallel converter, a notch filter is introduced in the outer voltage loop to prevent the ripple from entering the control loop, the specific order harmonic compensation is proposed in the inner current loop to reduce the grid current harmonics. For series converter, the dc-link voltage feedback is adopted to suppress the influence of voltage ripple on the compensation performance. Simulation and experimental results show that the grid current total harmonic distortion (THD) can be reduced effectively with the fixed dc-link capacitance compared with the traditional control strategy. The load voltage THD has also been reduced by more than half by the dc-link voltage feedback control. Moreover, with the smaller dc-link capacitance, single-phase UPQC can maintain better performance under the proposed control strategy.

The nearest level modulation (NLM)-based space vector pulse width modulation (SVPWM) algorithms have attracted a great deal of interest since they can provide various degrees of freedom, i.e., optimized switching sequences and adjustable duty cycles. This paper proposes a simplified three-dimensional (3-D) NLM-based SVPWM algorithm in a 3-D coordinate system. Compared with the generalized two-dimension (2-D) NLM-Based SVPWM schemes, the proposed method not only provides identical degrees of freedom to optimize switching patterns and obtain adjustable duty cycles, but also presents better digital implementation and lower hardware occupancy to achieve the real-time PWM generation. In addition, based on the NLM-based principle, a method of addressing the issue of unbalanced voltages in a three-phase 3-Level Neutral Point Clamped Cascaded Multilevel Converter (3LNPC-CMC) is introduced. The presented method possesses the optimized voltage balancing capacity and equalizes the unbalanced inner-cell and mutual-cell voltages in the 3LNPC-CMC with minimum number switching transition. Finally, the whole proposed process is verified by simulation and experimental results.

This study presents an active power filter (APF) based on diode‐clamped multilevel circuits with auxiliary dc‐link voltage balancing circuits and harmonic compensation control. The control algorithm is composed of indirect current loop for active and reactive power control, predictive current loop for harmonic filtering control and independent control for auxiliary balancing circuits. Among these modules, the indirect current along with the predictive current control will generate a combined voltage reference to the module of space vector pulse‐width modulation, which could output optimal modulation signals to the voltage control of a diode‐clamped multilevel converter. Comparing with traditional dc control for two‐level APF, this system takes advantages of indirect current control and multilevel circuits, including improvement in waveform quality, increase in system power rate and reduction in voltage stress and switching frequency on power semiconductors. Simulation and experimental results validate the effective control of the presented system.