This article presents a wireless neural implant with body-coupled (BC) data transmission and power delivery for freely behaving animals and incorporates a precision front end for high-quality neural recordings. The neural implant utilizes the body as a wireless transmission medium where it only needs small electrodes for data transmission and power delivery. An external device with patch electrodes can then be placed far away from the implant without the need for precise alignment. Furthermore, a four-channel continuous-time delta–sigma modulator (CT- $\Delta \Sigma \text{M}$ ) is integrated into the system for precision neural recordings. Each neural recording CT- $\Delta \Sigma \text{M}$ achieves an 82.3-dB signal-to-noise and distortion ratio (SNDR) and an 83.3-dB dynamic range (DR) while consuming only 8.6- $\mu \text{W}$ at a signal bandwidth of 10 kHz. The neural implant integrated circuit (IC) is fabricated in a 0.11- $\mu \text{m}$ CMOS with a high-density capacitor option, and the BC data receiver (RX) IC is implemented in a 0.18- $\mu \text{m}$ CMOS. The implant IC occupies a chip area of 4 $\text {mm}^{2}$ , including a 5-nF on-chip capacitor, and draws 280 $\mu \text{A}$ from a 2.3-V supply with a working data transmitter (TX) electrode. By exploiting direct-digital signaling for data transmission, the neural implant achieves a data rate of 20.48 Mb/s and a wireless power recovery of 644 $\mu \text{W}$ , resulting in an energy efficiency of 32 pJ/b. The entire neural implant system has been successfully verified by both electrical and in vivo measurements, while the wirelessly recorded electrocorticography (ECoG) signals with the prototype neural implant inside a rat demonstrate the end-to-end functionality of the proposed system.

We present an energy-efficient reception and transmission scheme based on the exploitation of the conductive properties of the body for wireless neural interface applications. High efficiencies were achieved with: 1) a three-level clock-embedded direct digital signaling scheme in the transmitter (TX) and 2) with a squaring clock extraction enabling data recovery scheme using a clocked-comparator in the receiver (RX). Additionally, the output voltage of the TX was boosted to secure the link budget of the RX. As a result, the RX and TX consumed 62 and 566 μW, respectively, for a rated output power of 185 μW and achieved a maximum data rate of 16.7 Mb/s. These operational characteristics corresponded to the energy consumptions of 3.7 pJ per received bit and 34 pJ per transmitted bit, demonstrating a promising potential for use in implanted devices.

This paper demonstrates body-coupled (BC) data transmission and multi-source power delivery systems for neural interface applications. The implanted data transmitter and power receiver utilize an electrode interface rather than an antenna or coil interface for battery-free wireless transmission, enabling the external data receiver and power transmitter with patch electrodes to be placed away from the implant without requiring precise alignment, which is a critical issue in the conventional communication modalities of inductive coupling. Significantly, the implanted power receiver produces the supply voltage using ambient body-coupled 50/60 Hz signals from the Mains, on top of the 40.68 MHz wireless power source from the external power transmitter, to increase the recovered power level and the voltage conversion efficiency (VCE). The body-coupled wireless systems for implanted and external devices are implemented with integrated circuits (ICs) fabricated in a 180 nm CMOS process. When 650 mVpp AC voltage is applied to the implanted device, the power receiver recovers up to 780 μW with ambient (60 Hz signals) BC energy harvesting, achieving 93% VCE, while 600 μW is recovered without ambient (60 Hz signals) signal. The recovered power supplies the regulated voltage to the direct-digital signaling transceiver, which consumes 460 μW with an uplink data rate of 10 Mbps and a downlink data rate of 200 kbps, corresponding to an energy efficiency of 46 pJ/b.

This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 μV_RMS, and the power consumption ranges from 4.5 to 19.4 μW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mV_PP, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through in vivo experiments using swine.

This paper presents 2‐channel time‐multiplexed chopper instrument amplifier for better gain accuracy and mismatch. Mostly, the current‐attenuated feedback resistor with a duty‐cycled resistor is adopted for boosting the RC time constant. It can achieve the high pass corner frequencies between 10 Hz and 320 Hz by a 3‐bit digitally controlled resistor bank of the attenuator. As a result, the instrument amplifier achieves 0.6% gain accuracy between two time‐multiplexed channels, 100 dB CMRR, ‐40 dB crosstalk, and noise densities of 50nV/√Hz. It is implemented in a 180‐nm CMOS technology. It occupies a 0.6 mm*0.6 mm chip area and consumes 1.5μA current consumption from a 1.8 V supply for each channel.

In this letter, the authors present a high‐efficiency AC‐to‐DC rectifier for a wireless power transmission system with an internal threshold voltage cancellation (IVC) scheme to improve power conversion efficiency (PCE) and voltage conversion ratio (VCR). The rectifier with the IVC scheme implemented in 0.18‐μm CMOS technology achieves a power efficiency of 86% at a resistive load of 510 Ω when a 13.56‐MHz AC signal with a 6‐V amplitude is applied. In contrast, a previous scheme shows a 58% PCE under the same condition.