A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption, The synthesis procedure is based on the relation between the ratio of the transconductance over de drain current g(m)/I-D and the normalized current I-D/(W/L). The g(m)/I-D indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models, The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA)

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Reducing absorber layer thickness below 500 nm in regular Cu(In,Ga)Se₂ (CIGS) solar cells decreases cell efficiency considerably, as both short‐circuit current and open‐circuit voltage are reduced because of incomplete absorption and high Mo/CIGS rear interface recombination. In this work, an innovative rear cell design is developed to avoid both effects: a highly reflective rear surface passivation layer with nano‐sized local point contact openings is employed to enhance rear internal reflection and decrease the rear surface recombination velocity significantly, as compared with a standard Mo/CIGS rear interface. The formation of nano‐sphere shaped precipitates in chemical bath deposition of CdS is used to generate nano‐sized point contact openings. Evaporation of MgF₂ coated with a thin atomic layer deposited Al₂O₃ layer, or direct current magnetron sputtering of Al₂O₃ are used as rear surface passivation layers. Rear internal reflection is enhanced substantially by the increased thickness of the passivation layer, and also the rear surface recombination velocity is reduced at the Al₂O₃/CIGS rear interface. (MgF₂/)Al₂O₃ rear surface passivated ultra‐thin CIGS solar cells are fabricated, showing an increase in short circuit current and open circuit voltage compared to unpassivated reference cells with equivalent CIGS thickness. Accordingly, average solar cell efficiencies of 13.5% are realized for 385 nm thick CIGS absorber layers, compared with 9.1% efficiency for the corresponding unpassivated reference cells. © 2014 The Authors. Progress in Photovoltaics: Research and Applications published by John Wiley & Sons Ltd.

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures