The gradually widening disparity in the speed of the CPU and memory has become a bottleneck for the development of chip multiprocessor (CMP) systems. Increasing penalties caused by frequent on-chip memory access have raised critical challenges in delivering high memory access performance with tight energy and latency budgets. To overcome the memory wall and energy wall issues, this paper adopts CMP systems with hybrid scratchpad memories (SPMs), which are configured from SRAM and nonvolatile memory. Based on this architecture, we propose two novel algorithms, i.e., energy-aware data allocation (EADA) and balancing data allocation to energy and write operations (BDAEW), to perform data allocation to different memories and task mapping to different cores, reducing energy consumption and latency. We evaluate the performance of our proposed algorithms by comparison with a parallel solution that is commonly used to solve data allocation and task scheduling problems. Experiments show the merits of the hybrid SPM architecture over the traditional pure memory system and the effectiveness of the proposed algorithms. Compared with the AGADA algorithm, the EADA and BDAEW algorithms can reduce energy consumption by 23.05% and 19.41%, respectively.
15 July 2016 in International Journal of Parallel Programming
Low-power and short-latency memory access is critical to the performance of chip multiprocessor (CMP) system devices, especially to bridge the performance gap between memory and CPU. Together with increased demand for low-energy consumption and high-speed memory, scratch-pad memory (SPM) has been widely adopted in multiprocessor systems. In this paper, we employ a hybrid SPM, composed of a static random-access memory (SRAM) and a nonvolatile memory (NVM), to replace the cache in CMP. However, there are several challenges related to the CMP that need to be addressed, including how to dynamically assign processors to application tasks and dynamically allocate data to memories. To solve these problems based on this architecture, we propose a novel dynamic data allocation and task scheduling algorithm, i.e., Dynamic Greedy Data Allocation and Task Scheduling (DGDATS). Experiments on DSP benchmarks demonstrate the effectiveness and efficiency of our proposed algorithms, namely, our proposed algorithm can generate a highly efficient dynamic data allocation and task scheduling approach to minimizing total execution cost and producing the least amount of write operations on NVMs. Our extensive simulation study demonstrates that our proposed algorithm exhibits excellent performance compared with the Heuristic Allocation (HA) and Adaptive Genetic Algorithm for Data Allocation (AGADA) algorithms. Based on the CMP systems with hybrid SPMs, DGDATS reduces the total execution cost by 22.18% and 51.37% compared to those of the HA and AGADA algorithms, respectively. Additionally, the average number of write operations on NVM is 19.82% lower than that of HA.
This paper addresses the feature selection problem for gene expression profiles. Feature selection based on fuzzy neighborhood rough sets is very important in gene expression profiles. The process of extracting key features in gene expression profiles may have two disadvantages: (1) it may generate many redundant features, thus reducing the classification accuracy, and (2) it may ignore some information. To address the above problems, this paper proposes a fuzzy neighborhood joint entropy model based on feature selection; this model adopts the nonnegative principle of fuzzy neighborhood joint entropy to evaluate the importance of a candidate feature gene. Based on the fuzzy neighborhood joint entropy model, this paper proposes a new feature gene selection algorithm: the fuzzy neighborhood joint entropy (FNJE) algorithm. In the model, first, fuzzy neighborhood particles and fuzzy decision-making are combined with the uncertainty measure of joint entropy to construct a fuzzy neighborhood joint entropy model. Second, the importance degree of a feature is introduced as the measurement standard of candidate feature genes to evaluate the importance of each feature. Third, the algorithm uses the importance of candidate features in selecting features to reduce the redundancy of the selected features and improve the classification accuracy. In this paper, based on the UCI and gene datasets, we conduct a series of experiments. The experimental results show that the proposed algorithm can select fewer feature genes and achieve higher classification accuracy. Compared with the other four algorithms, our proposed algorithm can improve the accuracy by 0.4 $$\%$$ $$-$$ 10.42 $$\%$$ and 1.16 $$\%$$ $$-$$ 15.18 $$\%$$ and can reach maximum accuracy values of 90.52 $$\%$$ and 87.02 $$\%$$ with the linear-SVM and KNN classifiers, respectively.
31 March 2020 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
With the advent of the Internet of Things (IoT), energy-harvesting nonvolatile processors (NVPs) have become promising platforms due to their durability when running on an intermittent power supply and fast read/write operations. However, the penalties caused by an increasing amount of data to be processed and growing communication demands pose critical challenges in the scheduling of tasks on energy-harvesting NVP platforms with tight energy and latency budgets. Together with the high power switching overhead that is induced under unstable power conditions, an increase in the amount of data to be processed significantly degrades the system performance. To overcome the problems of high communication and switching overheads for energy-harvesting NVP platforms, this article proposes a novel communication-aware task-scheduling technique. The algorithm first selects one or more executable tasks to be performed based on the task benefits and then calls a task partitioning algorithm to dynamically divide the scheduled tasks. We evaluate the performance of our proposed algorithm in comparison with the performance-aware task scheduling (PATH) and greedy iterative (GI) algorithms. Experimental results show that the proposed algorithm can reduce the execution time by 17.08% and 13.72% on average compared with the PATH and GI algorithms, respectively.