This paper presents the development of a novel surface plasmon polariton band-stop filter with tunable operating frequency. The tuning is done by embedding a high permittivity BST dielectric block into the gap of SPP transmission line (T-line). An obvious transmission dip at the certain frequency is observed due to Fabry-Pérot interference. The notch frequency is sensitive to the variation of the dielectric constant of the BST ceramic. Specifically, a transmission dip up to -11.5 dB is observed at the notch frequency of 8.12 GHz when the dielectric constant of BST is 425; the notch frequency shifts from 8.7 to 7.6 GHz when the dielectric constant of BST increases from 375 to 475. To further verify the functions of the proposed SPP filter, a prototype is fabricated on the Rogers-4003 dielectric substrate. The measured and the simulated results show good agreements. The proposed structure has outstanding features of a very compact area, simple fabrication, and tunable operating frequency, which have great potential for the applications in tunable frequency selection metamaterials devices.

Reconfigurable intelligent surfaces (RISs) are of potential use in 5G/6G wireless communications due to their tunable electromagnetic (EM) parameters for flexible beam manipulations. Two important parameters for RIS design are the reflection coefficient of the RIS element and the scattering pattern of the RIS. To realize rapid design of RISs, we propose a zero-pole-based multiport model to calculate the reflection coefficients and scattering patterns of RISs in this work. Specifically, the developed model establishes an accurate mapping relation between the element reflection coefficient and the loads on multiple internal ports by using the multiport S-parameter matrix. Additionally, the vector fitting method is employed to reduce the time cost of data acquisition for multiport S-parameters, in which a hybrid sampling scheme is employed to accelerate computation speed while keeping high accuracy. Using this model, we further develop an efficient far-field pattern prediction and synthesis algorithm for large-scale RIS design based on the antenna radiation superposition principle. The feasibility of the proposed model is demonstrated by an example of 3-bit RIS design, where the simulation results agree well with the measurement.

Compared with conventional analog circuit topology synthesis methods, the deep-reinforcement-learning-(DRL)-based method features much higher synthesis efficiency while possessing the merit of strong generalization capability. However, this method cannot synthesize operational amplifiers that involve signal division. To address this critical limitation, this paper presents new synthesis rules to guide the DRL-based synthesis process. In addition, to meet various design specifications requested by users, we further develop a smart circuit synthesis system, which can robustly return a solution (i.e., a feasible circuit topology with detailed device sizes) right away as long as the input design specifications are reasonable. A transfer learning scheme is proposed to reduce the computation overhead of training this system. The experimental results show the efficacy of our smart circuit synthesis system and transfer learning scheme, confirming an advancement over the state-of-the-art approaches.

A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain-frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P _{1 dB} are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm ² including all testing pads with a core size of only 0.105 mm ² . The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks.

This paper proposes a novel decoupling technique achieved by adjusting the position of feeding probes of antennas. Two inherent radiation modes (patch mode and monopole mode), with different patterns and polarizations, are simultaneously excited by the same feeding probe. High isolation is realized based on manipulating the relationship of two-mode couplings by moving the feeding positions. Since the two radiation modes are generated by the same antenna element, the proposed MIMO antenna features a simple structure and compact size. For verification, a two-element array with center-to-center spacing of 0.404 ${\lambda }_0$ (${\lambda }_0$ is the wavelength in the air) is prototyped and characterized. Simulation and experimental results show that the proposed novel technique can offer higher port isolation (>18.1 dB), increased efficiency (>70%), and a lower envelope correlation coefficient (ECC < 0.1) in the operating frequency band (11.61–12.49 GHz).