The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

Improved performance operational amplifier demand has continuously increased. IC designers use the charge pump technique as an advanced solution to implement the amplifier’s rail−to−rail input stage, but the need for a large load capacitor is a serious downside. To reduce this passive component value, high−frequency clock circuits with a 50% duty cycle should be implemented. This paper focuses on designing such a circuit that is further compensated with temperature and power supply, maintaining these performances even when process variations occur, starting from a ring oscillator as the architecture core. A pre−layout 50 MHz center frequency at 25 °C with a 1.6 temperature percentage error was achieved. Post−layout simulations to account for parasitic effects were also performed, with a 48.9 MHz center frequency reached. Distinct methods that control the frequency variation were discussed and established. Performance comparison of the designed PLL with previously reported clock circuits in the CMOS process was concluded, with superior results such as power consumption, die area, and temperature range accomplished.

Conventional operational amplifier designs often experience parameter performance issues during the transition between complementary input differential stages, which restricts the full rail-to-rail common mode voltage swing. This paper presents an innovative charge pump architecture featuring a feedback supply selector that optimizes the transition performance. The proposed approach employs a switched-capacitor technique to boost the supply voltage by 1.5 V relative to the input voltage, thereby enabling the use of a single pMOS differential input stage. The novel supply selector dynamically chooses the maximum available voltage between the external supply and the boosted output, ensuring efficient transistor switching and improved biasing. Schematic-level and post-layout simulations in a 250 nm CMOS process validate the design under varied load currents, supply voltages, temperatures, and process corners. Results show a significant reduction in output voltage ripple, with a maximum value of 48 mV achieved post-layout, and enhanced overall efficiency, even under higher load currents. This architecture provides a robust and scalable solution for advanced operational amplifiers, particularly in fields where high performance and stability are critical.

This paper presents a compact output-stage current-limiting architecture intended for reliable overcurrent protection in CMOS analog and mixed-signal circuits. In modern integrated systems, the output stages of blocks such as operational amplifiers, drivers, buffers, and reference circuits may be exposed to overload conditions, low-impedance loads, or short circuits that can lead to excessive power dissipation and device degradation. The proposed architecture employs scaled replicas of the output transistors together with local negative feedback to sense the delivered load current and independently limit both sinking and sourcing currents. The circuit is demonstrated by integration into a two-stage folded-cascode operational amplifier with a class-AB output stage and evaluated through circuit-level simulations in 130 nm CMOS technology. The results confirm a well-defined current limit across the supply and temperature corners that are relevant to high-reliability applications, spanning 2 V and 5 V supplies and a temperature range from −55 °C to 175 °C. The proposed current-limiting scheme constrains both pull-down and pull-up currents to approximately 9–12 mA across the investigated operating domain. Monte Carlo analysis further shows bounded dispersion and symmetric single-mode distributions, indicating predictable operation under device mismatch. These results demonstrate that the proposed architecture provides a compact and scalable solution for deterministic current limiting in reliability-critical CMOS systems.