High-k dielectric layers (HfSixOy and ZrO2) with different film morphologies were investigated by tunneling atomic-force microscopy (TUNA). Different current distributions were observed for amorphous and nanocrystalline films by analyzing TUNA current maps. This even holds for crystalline layers where highly resolved atomic-force microscopy cannot detect any crystalline structures. However, TUNA enables the determination of morphology in terms of differences in current densities between nanocrystalline grains and their boundaries. The film morphologies were proven by high-resolution transmission electron microscopy. The investigations show TUNA as powerful current mapping tool for the characterization of morphology in thin high-k films on a nanoscale.

The wide bandgap of silicon carbide (SiC) has attracted a large interest over the past years in many research fields, such as power electronics, high operation temperature circuits, harsh environmental sensing, and more. To facilitate research on complex integrated SiC circuits, ensure reproducibility, and cut down cost, the availability of a low-voltage SiC technology for integrated circuits is of paramount importance. Here, we report on a scalable and open state-of-the-art SiC CMOS technology that addresses this need. An overview of technology parameters, including MOSFET threshold voltage, subthreshold slope, slope factor, and process transconductance, is reported. Conventional integrated digital and analog circuits, ranging from inverters to a 2-bit analog-to-digital converter, are reported. First yield predictions for both analog and digital circuits show great potential for increasing the amount of integrated devices in future applications.

GaN epitaxially grown on Si is a material for power electronics that intrinsically shows a high density of dislocations. We show by Conductive Atomic Force Microscopy (C-AFM) and Defect Selective Etching that even for materials with similar total dislocation densities substantially different subsets of dislocations with screw component act as current leakage paths within the AlGaN barrier under forward bias. Potential reasons are discussed and it will be directly shown by an innovative experiment that current voltage forward characteristics of AlGaN/GaN Schottky diodes shift to lower absolute voltages when such dislocations are present within the device. A local lowering of the Schottky barrier height around conductive dislocations is identified and impurity segregation is assumed as responsible root cause. While dislocation related leakage current under low reverse bias could not be resolved, breakdown of AlGaN/GaN Schottky diodes under high reverse bias correlates well with observed conductive dislocations as measured by C-AFM. If such dislocations are located near the drain side of the gate edge, failure of the gate in terms of breakdown or formation of percolation paths is observed for AlGaN/GaN high electron mobility transistors.

In this work, an AlGaN/GaN-HEMT heterostructure is exemplarily studied by a strict place-to-place correlational approach in order to help clarify some open questions in the wide field of reliability topics. Especially, vertical leakage current, its relation to dislocations in general, and specific types in particular are investigated on a highly defective material. With the aid of atomic force microscopy (AFM) in tapping mode, cathodoluminescence imaging, defect selective etching, and energy dispersive X-ray, the material’s defect content around the device relevant two dimensional electron gas is analyzed. The total dislocation density, as well as the density of threading screw, edge, and mixed type dislocations, is systematically investigated directly. The obtained result is statistically much more significant than is possible by conventional transmission electron microscopy studies and more precise than the results obtained by the indirect method of rocking curve analysis. The method of conductive AFM allowed mapping of variations in the vertical leakage current, which could be correlated with variations in barrier leakage or gate leakage. Spots of locally high leakage current could be observed and directly assigned to dislocations with a screw component, but with significant differences even within the same group of dislocation types. The electrical activity of dislocations is discussed in general, and a fundamental model for a potential dislocation driven vertical leakage is proposed.

In this letter, we report on the reduction of device resistance by up to 36% in lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on a state-of-the-art LDMOS field-effect transistor with a reduced-surface-field extension (buried p-well) for high-voltage applications used for standard IC and ASIC manufacturing processes. Because the well implants can remain unchanged, only a few additional process steps are required for manufacturing such a device. By a straightforward combination of trench- with planar-gate topology, the device resistance can be reduced from 145 to 94 m¿·mm² for the underlying 50-V LDMOS device while fully maintaining its specified blocking properties. The depth of the trench gates just slightly influences the electrical device properties, demonstrating the robustness of trench-gate integration into an existing planar-gate technology.