Nilesh Goel

Dr. Nilesh Goel

orcid

Research Focus & Metrics

Academic Career Length

18Years (2009-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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22 January 2013 in IEEE Transactions on Electron Devices
Verified
Journal Article
Open access
SMS. Mahapatra
S. Mahapatra
NGNilesh Goel
Nilesh Goel
SDS. Desai
S. Desai
SGS. Gupta
S. Gupta
BJB. Jose
B. Jose
MAM. A. Alam
M. A. Alam
Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

21 December 2017 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
NPNarendra Parihar
Narendra Parihar
NGNilesh Goel
Nilesh Goel
SMSubhadeep Mukhopadhyay
Subhadeep Mukhopadhyay
SMSouvik Mahapatra
Souvik Mahapatra
A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc-ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

1 April 2012
Verified
Conference Paper
Closed access
KJKaustubh Joshi
Kaustubh Joshi
SMSubhadeep Mukhopadhyay
Subhadeep Mukhopadhyay
NGNilesh Goel
Nilesh Goel
SMSouvik Mahapatra
Souvik Mahapatra
A common framework of trap generation and trapping is used to explain Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) DC and AC stress/recovery data. NBTI is explained using trap generation in Si/SiON (IL) interface and SiON (IL) bulk, together with hole trapping in pre-existing bulk SiON (IL) traps. Interface trap generation and recovery can be fully explained using Reaction-Diffusion (RD) model. PBTI is explained using trap generation in SiON (IL)/HK interface and HK bulk, together with electron trapping in pre-existing bulk HK traps. Important similarities as well as differences between N and P BTI are highlighted.

4 February 2016 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
NPNarendra Parihar
Narendra Parihar
NGNilesh Goel
Nilesh Goel
ACAnkush Chaudhary
Ankush Chaudhary
SMSouvik Mahapatra
Souvik Mahapatra
A modeling framework is proposed to predict the degradation and recovery of threshold voltage shift (ΔV T ) due to negative bias temperature instability. Double interface reaction- diffusion model with transient trap occupancy model is used to predict the generation and recovery of interface traps (ΔV IT ). Empirical stretched exponential equations are used to capture hole trapping and detrapping in preexisting traps (ΔV HT ). The framework consists of uncoupled contributions from ΔV IT and ΔV HT and is capable of accurately predicting the ultrafast measured ΔV T during dc, arbitrary multicycle dc, ac, and mixed-mode dc-ac stress. It can predict pulse duty cycle and frequency dependence of ac degradation and also dynamic voltage and frequency scaling waveforms encountered in actual circuits.

1 June 2014
Verified
Conference Paper
Closed access
SMS. Mukhopadhyay
S. Mukhopadhyay
KJK. Joshi
K. Joshi
VCV. Chaudhary
V. Chaudhary
NGNilesh Goel
Nilesh Goel
SDS. De
S. De
SMS. Mahapatra
S. Mahapatra
Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (V G,STR ), time (t STR ) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to V T shift (ΔV T ) is compared to ΔV T from ultra-fast measurements. A compact model is used to predict overall BTI ΔV T considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.

1 March 2014 in Microelectronics Reliability
Verified
Journal Article
Closed access
NGNilesh Goel
Nilesh Goel
KJK. Joshi
K. Joshi
SMS. Mukhopadhyay
S. Mukhopadhyay
NNN. Nanaware
N. Nanaware
SMS. Mahapatra
S. Mahapatra