The vehicle testing–validation phase is a crucial and demanding task in the automotive development process for vehicle manufacturers. It ensures the correct operation, safety, and efficiency of the vehicle. To meet this demand, some commercial solutions are available on the market, but they are usually expensive, have few connectivity options, and are PC-dependent. This paper presents an IoT-based intelligent low-cost system for vehicle data acquisition during on-road tests as an alternative solution. The system integrates low-cost acquisition hardware with an IoT server, collecting and transmitting data in near real-time, while artificial intelligence (AI) algorithms process the information and report errors and/or failures to the manufacturing engineers. The proposed solution was compared with other commercial systems in terms of features, performance, and cost. The results indicate that the proposed system delivers similar performance in terms of the data acquisition rate, but at a lower cost (up to 13 times cheaper) and with more advanced features, such as near real-time intelligent data processing and reduced time to find and correct errors or failures in the vehicle.

A two‐phase colour‐aware real‐time scheduler to reduce the contention caused by the cache coherence protocol due to accesses to shared cache partitions in a multicore processor is proposed. The first phase is a colour‐aware task partitioning (CAP) algorithm that assigns tasks that share colours to a common processor whenever possible. The second phase is a dynamic colour‐aware scheduler that detects cache coherence activities at run‐time, preventing the execution of tasks that interfere with each other and thus reducing the contention caused by the cache coherence protocol. The authors compare the proposed scheduler with a CAP without run‐time optimisation and with the best‐fit decreasing heuristic in terms of deadline misses and tardiness of several task sets using a real‐time operating system and a modern 8‐core processor. The results indicate that the proposed scheduler improves deadline tardiness and provides hard real‐time guarantees by combining cache and task partitioning with scheduling optimisations.

Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard processing cores with programmable logic (PL) for high-performance computing applications. In this article, we take a deep look into these commercially available heterogeneous platforms and show how to design mixed-criticality applications such that different processing components can be isolated to avoid contention on the shared resources such as last-level cache and main memory. Our approach involves software/hardware co-design to achieve isolation between the different criticality domains. At the hardware level, we use a scratchpad memory (SPM) with dedicated interfaces inside the PL to avoid conflicts in the main memory. At the software level, we employ a hypervisor to support cache-coloring such that conflicts at the shared L2 cache can be avoided. In order to move the tasks in/out of the SPM memory, we rely on a DMA engine and propose a new CPU-DMA co-scheduling policy, called Lazy Load , for which we also derive the response time analysis. The results of a case study on image processing demonstrate that the contention on the shared memory subsystem can be avoided when running with our proposed architecture. Moreover, comprehensive schedulability evaluations show that the newly proposed Lazy Load policy outperforms the existing CPU-DMA scheduling approaches and is effective in mitigating the main memory interference in our proposed architecture.

Cache partitioning is a technique to reduce interference among tasks running on the processors with shared caches. To make this technique effective, cache segments should be allocated to tasks that will benefit the most from having their data and instructions stored in the cache. The requests for cached data and instructions can be retrieved faster from the cache memory instead of fetching them from the main memory, thereby reducing overall execution time. The existing partitioning schemes for real-time systems divide the available cache among the tasks to guarantee their schedulability as the sole and primary optimization criterion. However, it is also preferable, particularly in systems with power constraints or mixed criticalities where low- and high-criticality workloads are executing alongside, to reduce the total cache usage for real-time tasks. Cache minimization as part of design space exploration can also help in achieving optimal system performance and resource utilization in embedded systems. In this paper, we develop optimization algorithms for cache partitioning that, besides ensuring schedulability, also minimize cache usage. We consider both preemptive and non-preemptive scheduling policies on single-processor systems with fixed- and dynamic-priority scheduling algorithms (Rate Monotonic (RM) and Earliest Deadline First (EDF), respectively). For preemptive scheduling, we formulate the problem as an integer quadratically constrained program and propose an efficient heuristic achieving near-optimal solutions. For non-preemptive scheduling, we combine linear and binary search techniques with different fixed-priority schedulability tests and Quick Processor-demand Analysis (QPA) for EDF. Our experiments based on synthetic task sets with parameters from real-world embedded applications show that the proposed heuristic: (i) achieves an average optimality gap of 0.79% within 0.1× run time of a mathematical programming solver and (ii) reduces average cache usage by 39.15% compared to existing cache partitioning approaches. Besides, we find that for large task sets with high utilization, non-preemptive scheduling can use less cache than preemptive to guarantee schedulability.