The softmax function has been widely used in deep neural networks (DNNs), and studies on efficient hardware accelerators for DNN have also attracted tremendous attention. However, it is very challenging to design efficient hardware architectures for softmax because of the expensive exponentiation and division calculations in it. In this paper, the softmax function is firstly simplified by exploring algorithmic strength reductions. Afterwards, a hardware-friendly and precision-adjustable calculation method for softmax is proposed, which can meet different precision requirements in various deep learning (DL) tasks. Based on the above innovations, an efficient architecture for softmax is presented. By tuning the parameter P, the system accuracy and complexity can be adjusted dynamically to achieve a good tradeoff between them. The proposed design is coded using hardware description language (HDL) and evaluated on two platforms, Xilinx Zynq-7000 ZC706 development board and TSMC 28-nm CMOS technology, respectively. Hardware implementation results show that our architecture significantly outperforms other works in speed and area, and that by adjusting P, the accuracy can be further increased with little hardware overhead.

Recently, the layer-wise N:M fine-grained sparse neural network algorithm (i.e., every M-weights contains N non-zero values) has attracted tremendous attention, as it can effectively reduce the computational complexity with negligible accuracy loss. However, the speed-up potential of this algorithm will not be fully exploited if the right hardware support is lacking. In this work, we design an efficient accelerator for the N:M sparse convolutional neural networks (CNNs) with layer-wise sparse patterns. First, we analyze the performances of different processing element (PE) structures and extensions to construct the flexible PE architecture. Second, the variable sparse convolutional dimensions and sparse ratios are involved in the hardware design. With a sparse PE cluster (SPEC) design, the hardware can efficiently accelerate CNNs with the layer-wise N:M pattern. Finally, we employ the proposed SPEC into the CNN accelerator with flexible network-on-chip and specially designed dataflow. We implement hardware accelerators on Xilinx ZCU102 FPGA and Xilinx VCU118 FPGA and evaluate them with classical CNNs such as Alexnet, VGG-16, and ResNet-50. Compared with existing accelerators designed for structured and unstructured pruned networks, our design achieves the best performance in terms of power efficiency.

Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection process to increase potential profits. However, intensive computations and complicated data flow in the cointegration approach bring challenges to hardware acceleration. In this paper, for the first time, we propose an efficient and hardware-friendly computing scheme to accelerate the Engle-Granger cointegration. Besides, a novel algorithmic strength reduction strategy and approximation methods are used to significantly reduce the complexity of the proposed scheme. Based on the improved algorithm, both FPGA and ASIC accelerators are developed. The implementation results show that our FPGA and ASIC accelerators perform 36× and 207× faster than GPU, respectively. Thus, our design can significantly reduce the latency of the pairs selection process, and make more profit for investors and traders.

The Connectionist Temporal Classification (CTC) has achieved great success in sequence to sequence analysis tasks such as automatic speech recognition (ASR) and scene text recognition (STR). These applications can use the CTC objective function to train the recurrent neural networks (RNNs), and decode the outputs of RNNs during inference. While hardware architectures for RNNs have been studied, hardware-based CTC-decoders are desired for high-speed CTC-based inference systems. This paper, for the first time, provides a low-complexity and memory-efficient approach to build a CTC-decoder based on the beam search decoding. Firstly, we improve the beam search decoding algorithm to save the storage space. Secondly, we compress a dictionary (reduced from 26.02MB to 1.12MB) and use it as the language model. Meanwhile, we further enable searching this dictionary to be trivial. Finally, a fixed-point CTC-decoder for an English ASR and an STR task using the proposed method is implemented with C++ language. It is shown that the proposed method has little precision loss compared with its floating-point counterpart. Our experiments show that the compression ratio of the storage required by the proposed beam search decoding algorithm are 29.49 (ASR) and 17.95 (STR).

The accuracy of many natural language processing (NLP) tasks has been significantly improved with the development of deep learning and Transformer-based pre-trained models like BERT. However, their large number of parameters and computations pose deployment challenges. For instance, while using BERT can improve predictions in financial sentiment analysis (FSA) tasks, it can also slow down processing, where throughput and accuracy are equally important for profitability. To address these issues, we first propose an efficient and lightweight BERT model called ELBERT, which incorporates a novel confidence-window-based (CWB) early exit mechanism. In addition, an innovative approach is proposed to accelerate text processing on the GPU platform, which addresses the challenge of effectively deploying the early exit mechanism with large input batch sizes. Using these advancements, we develop a fast and high-accuracy FSA system. Experimental results demonstrate that the proposed CWB early exit mechanism outperforms existing early exit methods on BERT in terms of accuracy, at the same computation cost. By leveraging this acceleration method, our FSA system can boost the processing throughput by nearly 40 times, enabling it to process over 1000 texts per second with sufficient accuracy. This processing rate is nearly twice as fast as FastBERT, providing modern trading systems with a more powerful text processing capability.

Deep Research Agents (DRAs) generate detailed literature surveys but often suffer from hallucinations and inconsistent structures. Existing evaluation methods face significant limitations. Human evaluation is time-consuming and requires domain expertise. Meanwhile, current LLM judges struggle with long reports due to context limits and the inability to verify source reliability. To address this, we propose Deep-Research Eval. This framework standardizes the page as the basic unit for evaluation. It features an adaptive scoring system that assesses the logical quality of each page. Furthermore, it employs Paged-RAG with a constructible reference database to verify facts against specific evidence. Experiments on five agents show that our method effectively identifies errors. It achieves a strong correlation with human judgment, reaching a Composite Consistency Index (CCI) of 0.7585, an absolute increase of 0.4588 over baselines. Additionally, the Paged-RAG module improves factual verification accuracy, increasing the QA-F1 score by up to 6.9 times compared to standard retrieval methods. This work offers a scalable and practical approach for assessing AI-generated academic content.