This paper proposes a step-up 3-Ф switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology’s advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (V_DC), whereas the remaining switches experienced peak output voltage (2V_DC) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter’s theoretical justifications and real-time performance.

In this paper, some recently proposed multilevel power converters are investigated for their fault tolerant capabilities and improved reliability. These reported topologies are generally reduced device multilevel inverter (RD-MLIs) configurations that lack ability to tolerate switch failures due to absence of redundant states. Present work therefore aims to incorporate open circuit fault-tolerant capability by adding few redundant states in switching sequences of existing topologies. The work in this paper objectively presents two existing topologies of five-level and seven-level Multi Level Inverters (MLIs) modified for fault-tolerant (FT) capability against single switch open-circuit (OC) faults. The modification for fault-tolerant feature (FT-MLI) has intrinsic self-voltage balancing capability, low cost and control simplicity. The modified FT-MLI uses multi-carrier sinusoidal pulse-width modulation (SPWM) technique to generate control switching pulses as per desired switching sequences. Simulation and experimental results of these modified FT-MLI topologies under healthy, faulty and post fault mode are presented and discussed. Experimental results verify the feasibility and effectiveness of these modified FT-MLI topologies which are suitable for safety-critical applications.

In this paper, a higher level symmetrical and asymmetrical multilevel inverter (MLI) with reduced device count is proposed for renewable energy systems. Multilevel inverters are recently gaining importance in renewable energy systems and other DC to AC conversion applications due to reducing voltage stress, low total harmonic distortion (THD) and high-quality output as compared to classical inverters. This paper present a basic cell unit of reduced device count (RDC) MLI with six switching devices is proposed. The topology has advantages of reduced device count over existing topologies for the same number of output levels, thus improving operating efficiency and reliability. Upon cascading two such basic cells with 12 devices synthesizes a 49 level output with an estimated THD of 1.63%. The other advantages accrued due to reduced device count are a reduction in switch driver circuits, less number of required dc voltage sources, less installation space and reduction in cost. The major benefit of the proposed topology is that it can deliver power from an asymmetrical source to load even under sudden variation in environmental conditions. The proposed MLI topology is simulated in MATLAB/Simulink environment and a laboratory prototype is developed and tested in the lab. The control paradigm is developed as the Simulink model, which is interfaced with dSPACE DS-1104 for generating control pulses to drive switches of proposed MLI topology. The experimental results validate the concept and paradigm of the proposed MLI topology.