Wassim Khaddour

Mr. Wassim Khaddour

orcid

Research Focus & Metrics

Academic Career Length

7Years (2020-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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3 March 2023 in Sensors
Verified
Journal Article
Open access
PDF file
WKWassim Khaddour
Wassim Khaddour
WUWilfried Uhring
Wilfried Uhring
FDFoudil Dadouche
Foudil Dadouche
NDNorbert Dumas
Norbert Dumas
MMMADEC Morgan
MADEC Morgan
In this paper, two of the most common calibration methods of synchronous TDCs, which are the bin-by-bin calibration and the average-bin-width calibration, are first presented and compared. Then, an innovative new robust calibration method for asynchronous TDCs is proposed and evaluated. Simulation results showed that: (i) For a synchronous TDC, the bin-by-bin calibration, applied to a histogram, does not improve the TDC’s differential non-linearity (DNL); nevertheless, it improves its Integral Non-Linearity (INL), whereas the average-bin-width calibration significantly improves both the DNL and the INL. (ii) For an asynchronous TDC, the DNL can be improved up to 10 times by applying the bin–by-bin calibration, whereas the proposed method is almost independent of the non-linearity of the TDC and can improve the DNL up to 100 times. The simulation results were confirmed by experiments carried out using real TDCs implemented on a Cyclone V SoC-FPGA. For an asynchronous TDC, the proposed calibration method is 10 times better than the bin-by-bin method in terms of the DNL improvement.

1 June 2020
Verified
Conference Paper
Open access
WKWassim Khaddour
Wassim Khaddour
WUWilfried Uhring
Wilfried Uhring
FDFoudil Dadouche
Foudil Dadouche
VFVincent FRICK
Vincent FRICK
MMMorgan Madec
Morgan Madec
This work presents a Fluorescence Life-Time (FLT) measurement system for real-time microfluidic droplet sorting in high throughput conditions. This system is implemented using a low cost System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) platform, that combines a Cyclone V FPGA with a dual-core ARM Cortex-a9 Hard Processor System (HPS). A time-correlated single photon counting system is implemented in the FPGA part and the data are transferred to the SDRAM of the HPS part to be processed by a developed bare-metal C program to extract the FLT of each droplet passing through the detection spot. According to the droplet's measured FLT, an action could be taken to sort this droplet. The system automatically detects the droplets and extracts their FLT values at different simulated droplet flow rates; from a few droplets up to 1 thousand droplets per second. Thanks to the use of a maximum Likelihood-based algorithm, the standard deviation of the measured FLTs of simulated droplets of the same material is only 30% above the theoretical quantum photon shot noise limit.