Hardware security for an Internet of Things (IoT) or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the N-cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term effects of a slight modification of the seed (proven to be sensitive to the initial conditions) or of the inputted generator cannot be predicted. The proposal has been fully deployed on a FPGA and 65nm ASIC, it runs completely in parallel while consuming as low resources as possible, and achieving: (a) 11.5 Gbps for FPGA and 9.4 Gbps for ASIC random bit throughput, (b) 3.3μ W (LF) to 7.8 mW (UHF) total power consumption with 5% leakage power, measured at 1.32V, and (c) able to successfully pass the statistical tests of NIST and TestU01 (BigCrush).

Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of area, throughput, and statistical tests, is performed. The hardware pseudorandom number generation can reach a throughput/latency ratio equal to 8.5 Gbps for Zynq-FPGA and 10.9 Gbps for ASIC, being thus the fastest FPGA generators based on chaos that can pass TestU01. In particular, it is established that CIPRNG-XOR is $2.5$ times faster and 5 times more efficient that almost all linear PRNGs who pass TestU01.