Hardware solutions for malware detection are becoming increasingly important as software-based solutions can be easily compromised by intelligent malware. However, the cost of hardware solutions including design complexity and dynamic power consumption cannot be ignored. Many of the existing hardware solutions are based on statistical learning blocks with abnormal features of system calls, network traffics, or processor behaviors. Among those solutions, the performance of the learning techniques relies primarily on the quality of the training data. However, for the processor behavior-based solutions, only a few behavioral events can be monitored simultaneously due to the limited number of PMCs (Performance Monitoring Counters) in a processor. As a result, the quality and quantity of the data obtained from architectural features have become a critical issue for PMC-based malware detection. In this paper, to emphasize the importance of selecting architectural features for malware detection, the statistical differences between malware workloads and benign workloads were characterized based on the information from performance counters. Most malware can easily be detected with basic characteristics, but some malware types are statistically very similar to benign workloads which need to be handled more in-depth. Hence, we focus on multiple steps to investigate critical issues of PMC-based malware detection: (i) statistical characterization of malware; (ii) distribution-based feature selection; (iii) trade-off analysis of detection time and accuracy; and (iv) providing architectural design alternatives for hardware-based malware detection. Our results show that the existing number of performance counters is not enough to achieve the desired accuracy. For more accurate malware detection in real-time, we propose both accuracy improvement schemes (with additional PMCs, etc.) and hardware acceleration schemes. Both schemes provide accuracy improvement (5~10%) and detection speedup (up to 10%) with the additional hardware cost (less than 1% of the chip complexity).

Deep learning and neural networks have become increasingly popular in the area of artificial intelligence. These models have the capability to solve complex problems, such as image recognition or language processing. However, the memory utilization and power consumption of these networks can be very large for many applications. This has led to research into techniques to compress the size of these models while retaining accuracy and performance. One of the compression techniques is the deep compression three-stage pipeline, including pruning, trained quantization, and Huffman coding. In this paper, we apply the principles of deep compression to multiple complex networks in order to compare the effectiveness of deep compression in terms of compression ratio and the quality of the compressed network. While the deep compression pipeline is effectively working for CNN and RNN models to reduce the network size with small performance degradation, it is not properly working for more complicated networks such as GAN. In our GAN experiments, performance degradation is too much from the compression. For complex neural networks, careful analysis should be done for discovering which parameters allow a GAN to be compressed without loss in output quality.

Traveling-wave tube amplifiers are widely used in satellite communication systems, but introduce severe intermodulation distortion when operated at peak efficiency. In this paper, we examine the performance of fully-coupled and partially-decoupled LMS adaptive Volterra equalizers in mitigating intersymbol interference in digitally-modulated signals subject to this distortion in bent-pipe satellite communication systems (i.e., systems in which equalization takes place in the receiver). Adaptive Volterra equalization was found to be more effective than linear equalization alone when channel memory is relatively low and signal-to-distortion ratio is relatively high. The adaptive Volterra equalizer was found to match the nonlinear channel more closely than a conventional receiver matched filter. While linear and cubic Volterra kernels are needed for equalization of M -PSK modulation schemes, inclusion of a quintic kernel did not significantly help in equalizing BPSK, QPSK, or 8-PSK, but slightly improved equalization of 16-QAM (~0.5dB at 3dB IBO) over and above that obtained with linear and cubic kernels. Using typical to severe values for channel memory, optimum linear equalizer memory for BPSK was found to be four; no optimum cubic memory length was found. Optimum memory for equalization of QPSK, 8-PSK, and 16-QAM was found to be four linear and four or five cubic memory units. Difference in performance between fully-coupled and partially-decoupled adaptive equalizers was found to be small, rarely exceeding ~1.5dB mean-square error. Because implementation of any Volterra filter incurs a high computational burden, there is great incentive to increase computational efficiency. Three practical strategies for increasing computational efficiency were explored: convolution-sum factoring, elimination of redundant kernel coefficients by symmetry restriction, and use of “simplified” kernels containing relatively few cubic and/or quintic coefficients. These strategies make implementation of a Volterra equalizer on an FPGA feasible. Exact polynomial expressions in memory units for computational burden were derived for these efficient forms.

Deep neural networks (DNNs) have several technical issues on computational complexity, redundancy, and the parameter size – especially when applied in embedded devices. Among those issues, lots of parameters require high memory capacity which causes migration problem to embedded devices. Many pruning techniques are proposed to reduce the network size in deep neural networks, but there are still various issues that exist for applying pruning techniques to DNNs. In this paper, we propose a simple-yet-efficient scheme, accuracy-aware structured pruning based on the characterization of each convolutional layer. We investigate the accuracy and compression rate of individual layer with a fixed pruning ratio and re-order the pruning priority depending on the accuracy of each layer. To achieve a further compression rate, we also add quantization to the linear layers. Our results show that the order of the layers pruned does affect the final accuracy of the deep neural network. Based on our experiments, the pruned AlexNet and VGG16 models’ parameter size is compressed up to 47.28x and 35.21x with less than 1% accuracy drop with respect to the original model.