Moving transistors downscale: One option for extending the performance of complementary metal-oxide semiconductor (CMOS) devices based on silicon technology is to use semiconducting carbon nanotubes as the gates. Qiu et al. fabricated top-gated carbon nanotube field-effect transistors with a gate length of 5 nm. Thin graphene contacts helped maintain electrostatic control. A scaling trend study revealed that, compared with silicon CMOS devices, the nanotube-based devices operated much faster and at much lower supply voltage, and they approached the limit of one electron per switching operation. Science , this issue p. 271

Aligning dense carbon nanotube arrays: Although semiconducting carbon nanotubes (CNTs) are promising candidates to replace silicon in transistors at extremely small dimensions, their purity, density, and alignment must be improved. Liu et al. combined a multiple dispersion sorting process, which improves purity, and a dimension-limited self-alignment process to produce well-aligned CNT arrays on a 10-centimeter silicon wafer. The density is sufficiently high (100 to 200 CNTs per micrometer) that large-scale integrated circuits could be fabricated. With ionic liquid gating, the performance metrics exceeded those of conventional silicon transistors with similar dimensions. Science , this issue p. 850

Cooler electrons for transistors: The operating power of field-effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts. Science , this issue p. 387