This article proposes a new low-impedance transient-current enhanced (LTE) buffer, which is applied for low-dropout regulator (LDO) with large off-chip capacitor. The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output impedance and high charging/discharging current of the gate of power transistor at load transient response, while maintaining low-quiescent current consumption under the full-load range. In addition to containing the LTE buffer, the proposed LTE-LDO employs recycling-folded-cascode amplifier as the error amplifier, which has the advantage of high loop gain, loop bandwidth, and current efficiency. Meanwhile, simple Miller compensation with a nulling resistor is employed for frequency compensation and a complete small-signal analysis under different load current conditions is given in this article. This design has been implemented in semiconductor manufacturing international corporation 0.18 $\mu$ m complementary metal–oxide–semiconductor process and the experimental results show that the quiescent current consumption is about 48 $\mu$ A, and the maximum current efficiency of the LTE-LDO is 99.976 $\%$ . The measured transient response shows that under the condition of 1 $\mu$ F load capacitance, when the load current changes to 200 mA/100 ns, the output voltage change is 76 mV.

In this study, a local positive feedback technique is proposed to enhance the performance of the folded cascode (FC) operational transconductance amplifier (OTA) when working in its saturation region. The enhanced FC-OTA has a higher gain bandwidth (GBW), higher DC gain and higher slew rate (SR) over its conventional counterparts and popular recycling FC-OTAs. The proposed enhanced FC-OTA is implemented by reusing the current generated by the input transistors through the proposed local positive feedback loop to provide additional transconductance and negative resistance. It is then fabricated with SMIC 180nm process. To verify the effectiveness of the proposed FC-OTA performance enhancement strategy, extensive mathematical analysis, small-/large-signal stability analysis, simulation and experimentation are thoroughly investigated in this study. Simulation and experimental results agree well with the theoretical analysis and the expected performances, which corroborates the control design.

An adaptively biased low dropout regulator (ABLDO) with current mirror buffer has been proposed in previous literatures, which only solves a few of specific problems of AB-LDO without additional synthetical analysis of the various performances. Based on the analysis, it is found that enhancing the current efficiency of operational transconductance amplifier (OTA) is a key factor to improve the performances of ABLDO. And a current reusing current-mode OTA (CRCM-OTA) with high current efficiency is proposed to apply to AB-LDO. Compared with the traditional AB-LDO, it can achieve an obvious improvement of AB-LDO performances including the current efficiency of AB-LDO, loop gain and loop bandwidth without increasing the area and power consumption. This paper also adopts an intuitive method different from the previous works to analyze the whole loop. The AB-LDO using an advanced CRCM-OTA was fabricated in SMIC 0.18μm CMOS process, which has a transient undershoot of 26.25mV with an output capacitor of 1μF for a load step of 0-50mA with edge time of 10ns and realizes a performance figure of merit (F oM) value of 13.65ps.

Adaptive bias scheme, which can be used to provide a current proportional to the current flowing through the power transistor under high current load, avoiding the need for providing additional large fixed bias current to the circuit, has been adopted in many low-dropout regulators (LDO). When an adaptive bias scheme is applied to an LDO with a current mirror buffer, although a low chip area consumption and a better transient response can be achieved, the loop gain of LDO at high-load current and loop bandwidth at low load are still low. In previous works, multiple small-gain stages can effectively improve the gain and bandwidth but may lead to stability problems or even need to consume large currents to ensure stability, thus affecting current efficiency. This article proposes the multiple adaptive current feedbacks technique for small-gain stages in adaptively biased low dropout regulator (AB-LDO) with a current mirror buffer, improving the loop gain and bandwidth and eliminating the need for frequency compensation to meet stability requirements. Moreover, in the case that multiple adaptive bias loops can be introduced after the proposed technique is applied to this design, an intuitive and simple method is adopted to analyze the whole circuit. The designed AB-LDO was fabricated in Semiconductor Manufacturing International Corp (SMIC) 0.18- $\mu$ m process. The measured results show that the designed LDO realizes 30.75-mV transient performances with a step of 10 ns.

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a 0.18 μm CMOS technology and the chip area of it is about 0.076mm2. The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3∘, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/μs average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only 108μW, proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.

An adjustably transconductance enhanced bulk‐driven operational transconductance amplifier (OTA) working at weak inversion region is presented. Based on the traditional positive feedback source degeneration technique, a proposed current‐shunt auxiliary amplifier is employed here to modulate the gate of input differential pairs, achieving a further improvement of the effective transconductance with the CMOS technologies scaling. In addition, an adjustable transconductance enhancement factor is obtained, leading to an enhanced stability performance. Both conventional and proposed bulk‐driven OTAs are designed and simulated on CSMC 180 nm process. The simulated results demonstrate that the unity gain‐bandwidth of the proposed bulk‐driven OTA is improved by 120% compared to that of the conventional counterpart with a little neglected increased power consumption.