This paper presents interactive power electronics educational tools. These interactive tools make use of the benefits of Java language to provide a dynamic and interactive approach to simulating steady-state ideal rectifiers (uncontrolled and controlled; single-phase and three-phase). Additionally, this paper discusses the development and use of Java applet programs to assist the teaching of conventional power electronics rectifier circuits and to serve as a first design tool for basic laboratory experiments in power electronics courses. Comparison was made among results obtained using a well-known simulator package, experimental results, and the developed interactive simulation applets in order to validate the latter.

After years of dormant scenario, the Brazilian industry of photovoltaic (PV) energy systems is now growing fast. Therefore, improving interconnection and certification codes, as well as standards, has become undeniably important to establish a well-regulated market under concern of businesses, equipment and power quality matters. Thus, considering international standards and world-recognized scenarios for distributed PV systems, this paper aims to discuss the existing local energy regulations, grid connection codes, and other related limitations that restrain a faster market and technology development in Brazil. Special attention is given to the certification requirements for grid-connected inverters and other PV equipment, along with the new trends in energy policies, focusing on their impacts on Brazilian PV industry. In the end, it demonstrates that despite its current underdeveloped status, the Brazilian scenario is expected to be quite enthusiastic in the following years and may represent an attractive and dynamic market for professionals, companies and energy investors.

This paper presents the comparison of three topologies of multilevel inverters applied to drive an induction motor of 500 kVA/4.16 kV. The multilevel inverters analyzed are: a neutral point clamped inverter, a symmetrical cascaded multilevel inverter and a hybrid asymmetrical cascaded multilevel inverter. The performance indexes used in the comparison are total harmonic distortion, first order distortion factor, semiconductors power losses distribution and heat-sink volume. The comparison is developed with the purpose of finding the efficiency and the heat-sink volume where the three systems present the same output filter.

This paper presents a 2 kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by field programmable gate array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2 kW implemented prototype with four interleaved cells, 400 V nominal output voltage and 220 V_rms nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device