With the miniaturization of digital integrated circuits, electronic systems with increased functionality and enhanced performance are preferred. Multi-valued logic design is a promising alternative that offers a higher number of data/information which leads to energy efficiency, higher information density and reduced circuit overheads in terms of interconnect complexity. Hence in this work multi-valued logic design benefits of increased computational capability and reduced interconnect complexity are being explored for the implementation of sequential elements viz. ternary shift registers. Carbon nanotube field-effect transistors(CNTFETs) unique feature of alteration of threshold voltage by variations in CNT diameter further favor its suitability to implement ternary logic designs. Here single-edge triggered ternary shift registers design methodology is presented using multiplexer based D-flip-flop cells. The design of D-flip-flops is performed using multiplexer based positive and negative latches. After this series connection of D-flip-flop is performed to construct serial input serial output and parallel input serial output registers. The parallel input serial output registers can operate in two modes of loading and shifting and three different configurations of AND-OR logic, NAND logic and latch based selection circuitry are proposed. For performance analysis Synopsis HSPICE simulations are conducted using the 32nm CNTFET Stanford model. According to simulation results, for the proposed ternary shift registers maximum reduction in power consumption and energy consumption of more than 80% are obtained as compared to recent counterparts.