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Kea-Tiong Tang
Faculty of Electrical Engineering National Tsing Hua University (NTHU) Hsinchu Taiwan

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Original research paper
Published: 28 July 2021 in Electronics Letters
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This letter presents an upgraded winner-take-all (WTA) circuit that is capable of operating under low-voltage supplies. The proposed circuit re-configures the basic loop of a conventional WTA through an auxiliary transistor to decrease the dropped voltage across the tail current. This reconfiguration creates an additional biasing voltage providing more adjustability. Moreover, the new feedback path decreases the delay compared to the conventional WTA. Both conventional and proposed WTAs were fabricated in the TSMC 0.18 μm CMOS technology. The experimental results show a 29.4 and 33.2 μs reduction in rising and falling times, respectively, for the proposed WTA under a supply voltage of 0.3 V.

ACS Style

Meysam Akbari; Ting‐I Chou; Kea‐Tiong Tang. An adjustable 0.3 V current winner‐take‐all circuit for analogue neural networks. Electronics Letters 2021, 1 .

AMA Style

Meysam Akbari, Ting‐I Chou, Kea‐Tiong Tang. An adjustable 0.3 V current winner‐take‐all circuit for analogue neural networks. Electronics Letters. 2021; ():1.

Chicago/Turabian Style

Meysam Akbari; Ting‐I Chou; Kea‐Tiong Tang. 2021. "An adjustable 0.3 V current winner‐take‐all circuit for analogue neural networks." Electronics Letters , no. : 1.

Journal article
Published: 10 June 2021 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier's specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18-μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

ACS Style

Meysam Akbari; Safwan Mawlood Hussein; Yasir Hashim; Kea-Tiong Tang. An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2021, 29, 1601 -1611.

AMA Style

Meysam Akbari, Safwan Mawlood Hussein, Yasir Hashim, Kea-Tiong Tang. An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2021; 29 (9):1601-1611.

Chicago/Turabian Style

Meysam Akbari; Safwan Mawlood Hussein; Yasir Hashim; Kea-Tiong Tang. 2021. "An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, no. 9: 1601-1611.

Journal article
Published: 07 May 2021 in IEEE Journal of Solid-State Circuits
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This article presents a low-power, high-speed smart vision sensor for motion detection (MD) that realizes in-pixel frame-difference (FD) operation using a global shutter mechanism. A ping-pong pulse-width-modulation (PWM) pixel is proposed to achieve the consecutive event frame report with a balanced signal transfer function of successive FD operations. Three operating modes were implemented for varied application scenarios, such as image capture (IC) mode to capture a raw image, FD mode for MD, and saliency detection (SD) mode for low-resolution sub-block event counting. A 0.8 V 64 x 64 vision sensor prototype was fabricated and verified in TSMC 0.18-μm standard CMOS technology. In IC mode, it consumed 71.2 μ[email protected] with an achieved iFoM of 48.3 pJ/pixel· frame. In FD mode, it consumed 74.4 μ[email protected] with full-resolution (64 x 64) event reporting and achieved iFoMs of 35.6 pJ/pixel· frame. In SD mode, it consumed 121.6 μ[email protected] with block-level (8 x 8) saliency reporting and achieved iFoMs of 2.1 nJ/block· frame.

ACS Style

Tzu-Hsiang Hsu; Yen-Kai Chen; Min-Yang Chiu; Guan-Cheng Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh. A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. IEEE Journal of Solid-State Circuits 2021, 56, 2516 -2524.

AMA Style

Tzu-Hsiang Hsu, Yen-Kai Chen, Min-Yang Chiu, Guan-Cheng Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh. A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. IEEE Journal of Solid-State Circuits. 2021; 56 (8):2516-2524.

Chicago/Turabian Style

Tzu-Hsiang Hsu; Yen-Kai Chen; Min-Yang Chiu; Guan-Cheng Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh. 2021. "A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel." IEEE Journal of Solid-State Circuits 56, no. 8: 2516-2524.

Journal article
Published: 27 April 2021 in IEEE Journal of Solid-State Circuits
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This article presents a computing-in-memory (CIM) structure aimed at improving the energy efficiency of edge devices running multi-bit multiply-and-accumulate (MAC) operations. The proposed scheme includes a 6T SRAM-based CIM (SRAM-CIM) macro capable of: 1) weight-bitwise MAC (WbwMAC) operations to expand the sensing margin and improve the readout accuracy for high-precision MAC operations; 2) a compact 6T local computing cell to perform multiplication with suppressed sensitivity to process variation; 3) an algorithm-adaptive low MAC-aware readout scheme to improve energy efficiency; 4) a bitline header selection scheme to enlarge signal margin; and 5) a small-offset margin-enhanced sense amplifier for robust read operations against process variation. A fabricated 28-nm 64-kb SRAM-CIM macro achieved access times of 4.1-8.4 ns with energy efficiency of 11.5-68.4 TOPS/W, while performing MAC operations with 4- or 8-b input and weight precision.

ACS Style

Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Nan-Chun Lien; Wei-Chiang Shih; Yajuan He; Qiang Li; Meng-Fan Chang. A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE Journal of Solid-State Circuits 2021, 56, 2817 -2831.

AMA Style

Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang. A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE Journal of Solid-State Circuits. 2021; 56 (9):2817-2831.

Chicago/Turabian Style

Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Nan-Chun Lien; Wei-Chiang Shih; Yajuan He; Qiang Li; Meng-Fan Chang. 2021. "A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips." IEEE Journal of Solid-State Circuits 56, no. 9: 2817-2831.

Journal article
Published: 14 December 2020 in IEEE Transactions on Circuits and Systems II: Express Briefs
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This paper presents an adjustable third-order filter without employing passive elements. The proposed filter combines two low-pass and band-pass MOSFET-only topologies to configure a dual-output structure, while the transconductances and parasitic gate-source capacitances of the transistors act as the required passive elements. The main core of the proposed filter contains just 3 transistors that with the elimination of passive elements results in a small silicon area and low power consumption. The proposed filter benefits from low-input and high-output impedances that is an advantage for cascading in current-mode systems. Moreover, a kind of self-biasing topology is used to configure the proposed filter in which a control voltage is provided to move the center frequency of both outputs in a wide frequency range. The proposed circuit was fabricated using TSMC 0.18 μm CMOS process. Experimental and simulation results at a supply voltage of 1.8 V show a bandwidth range from 38.1 MHz to 99.5 MHz for a capacitive load bigger than 15 pF, while the average power consumption is 435 μW. It occupies a silicon area of just 43 μm × 86 μm.

ACS Style

Meysam Akbari; Safwan Mawlood Hussein; Yasir Hashim; Kea-Tiong Tang. An Adjustable Dual-Output Current Mode MOSFET-Only Filter. IEEE Transactions on Circuits and Systems II: Express Briefs 2020, 68, 1817 -1821.

AMA Style

Meysam Akbari, Safwan Mawlood Hussein, Yasir Hashim, Kea-Tiong Tang. An Adjustable Dual-Output Current Mode MOSFET-Only Filter. IEEE Transactions on Circuits and Systems II: Express Briefs. 2020; 68 (6):1817-1821.

Chicago/Turabian Style

Meysam Akbari; Safwan Mawlood Hussein; Yasir Hashim; Kea-Tiong Tang. 2020. "An Adjustable Dual-Output Current Mode MOSFET-Only Filter." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 6: 1817-1821.

Journal article
Published: 16 November 2020 in IEEE Sensors Journal
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ACS Style

Syuan-He Wang; Ting-I Chou; Shih-Wen Chiu; Kea-Tiong Tang. Using a Hybrid Deep Neural Network for Gas Classification. IEEE Sensors Journal 2020, 21, 6401 -6407.

AMA Style

Syuan-He Wang, Ting-I Chou, Shih-Wen Chiu, Kea-Tiong Tang. Using a Hybrid Deep Neural Network for Gas Classification. IEEE Sensors Journal. 2020; 21 (5):6401-6407.

Chicago/Turabian Style

Syuan-He Wang; Ting-I Chou; Shih-Wen Chiu; Kea-Tiong Tang. 2020. "Using a Hybrid Deep Neural Network for Gas Classification." IEEE Sensors Journal 21, no. 5: 6401-6407.

Journal article
Published: 06 November 2020 in IEEE Journal of Solid-State Circuits
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As the growing demand on artificial intelligence (AI) Internet-of-Things (IoT) devices, smart vision sensors with energy-efficient computing capability are required. This article presents a low-power and low-voltage dual mode 0.5-V computational CMOS image sensor (C²IS) with array-parallel computing capability for feature extraction using convolution. In the feature extraction mode, by applying the pulsewidth modulation (PWM) pixel and switch-current integration (SCI) circuit, the in-sensor eight-directional matrix-parallel multiply-accumulate (MAC) operation is realized. Furthermore, the analog-domain convolution-on-readout (COR) operation, the programmable 3 x 3 kernel with ±3-bit weights, and the tunable-resolution column-parallel analog-to-digital converter (ADC) (1-8 bit) are implemented to achieve the real-time feature extraction without using additional memory and sacrificing frame rate. In the image capturing mode, the sensor provides the linear-response 8-bit raw image data. The C²IS prototype has been fabricated in the TSMC 0.18-μm standard process technology and verified to demonstrate the raw and feature images at 480 frames/s with a power consumption of 77/117 μW and the resultant FoM of 9.8/14.8 pJ/pixel/frame, respectively. The prototype sensor is used as a real-time edge feature detection frond-end camera and accompanied with a simplified convolutional neural network (CNN) architecture to demonstrate the hand gesture recognition. The prototype system achieves more than 95% validation accuracy.

ACS Style

Tzu-Hsiang Hsu; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh. A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. IEEE Journal of Solid-State Circuits 2020, 56, 1588 -1596.

AMA Style

Tzu-Hsiang Hsu, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh. A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. IEEE Journal of Solid-State Circuits. 2020; 56 (5):1588-1596.

Chicago/Turabian Style

Tzu-Hsiang Hsu; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh. 2020. "A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction." IEEE Journal of Solid-State Circuits 56, no. 5: 1588-1596.

Journal article
Published: 30 September 2020 in IEEE Sensors Letters
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The practical use of electronic nose (e-nose) systems suffers from drift issue, which alters data distribution and reduces the accuracy of classification. This work proposes a transfer learning method called concentration-based drift calibration (CDC) for calibrating the sensor drift. Based on the sensor characteristic that sensor response is correspondent to gas concentration, transfer samples were collected in the target domain for certain gas concentrations, and then used for calibration with a designed concentration-based (CB) model and CDC transfer process. This method was evaluated on a complex time-varying drift dataset. The experimental results show that the proposed method for drift calibration is effective, and can be used for real-world applications. Moreover, the CDC transfer process can be applied over time with data that has been previously collected to yield a more generalized model.

ACS Style

Yu-Chieh Cheng; Ting-I. Chou; Shih-Wen Chiu; Kea-Tiong Tang. A Concentration-Based Drift Calibration Transfer Learning Method for Gas Sensor Array Data. IEEE Sensors Letters 2020, 4, 1 -4.

AMA Style

Yu-Chieh Cheng, Ting-I. Chou, Shih-Wen Chiu, Kea-Tiong Tang. A Concentration-Based Drift Calibration Transfer Learning Method for Gas Sensor Array Data. IEEE Sensors Letters. 2020; 4 (10):1-4.

Chicago/Turabian Style

Yu-Chieh Cheng; Ting-I. Chou; Shih-Wen Chiu; Kea-Tiong Tang. 2020. "A Concentration-Based Drift Calibration Transfer Learning Method for Gas Sensor Array Data." IEEE Sensors Letters 4, no. 10: 1-4.

Journal article
Published: 21 July 2020 in IEEE Access
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For electronic nose systems to obtain meaningful information from sensor data, sensor response features are first extracted for further signal processing. However, redundant features may diminish the accuracy of gas classification. To solve this problem, a minimum distance inlier probability (MDIP) feature selection (FS) method is proposed. By incorporating the intrinsic properties of features and ranking strategy, MDIP can efficiently eliminate redundant features and provide better classification accuracy. The performance of the method was validated on two open-access datasets that provide information for system variation and sensor drift problems, respectively. Experimental results revealed that the average classification accuracy for the two datasets was higher by 46.1% and 37.5%, respectively, with the MDIP method.

ACS Style

Yen-Tung Liu; Kea-Tiong Tang. A Minimum Distance Inlier Probability (MDIP) Feature Selection Method to Improve Gas Classification for Electronic Nose Systems. IEEE Access 2020, 8, 133928 -133935.

AMA Style

Yen-Tung Liu, Kea-Tiong Tang. A Minimum Distance Inlier Probability (MDIP) Feature Selection Method to Improve Gas Classification for Electronic Nose Systems. IEEE Access. 2020; 8 (99):133928-133935.

Chicago/Turabian Style

Yen-Tung Liu; Kea-Tiong Tang. 2020. "A Minimum Distance Inlier Probability (MDIP) Feature Selection Method to Improve Gas Classification for Electronic Nose Systems." IEEE Access 8, no. 99: 133928-133935.

Journal article
Published: 16 July 2020 in IEEE Transactions on Circuits and Systems I: Regular Papers
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This study proposes an output capacitor-less linear regulator with high power supply rejection (PSR) for a wireless power transmission system. To achieve high PSR with a noisy input voltage, a fully integrated linear regulator with its reference circuit supplied by the output voltage is proposed. The proposed technique can isolate the reference circuit from the noisy VIN, thereby reducing the requirements of the conventional bulky low-pass filter loading the reference voltage node while achieving superior PSR performance. The regulator uses an N-type pass transistor and a dual-feedback structure to achieve wideband ripple-filtering and fast transient responses. The proposed regulator is compatible with typical biomedical implants requiring a 10mA load current at 1.1V output voltage while consuming a total quiescent current of 276μ A. A PSR performance was measured to be -48 and - 56 dB against the VIN and charge pump at 10 MHz, respectively. The unity gain bandwidth (UGB) of the regulator was 291MHz. The proposed regulator was fabricated using commercial TSMC 0.18-μm CMOS technology with an area of 0.1054 mm² including the reference circuit.

ACS Style

Yan-Peng Chen; Kea-Tiong Tang. A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference. IEEE Transactions on Circuits and Systems I: Regular Papers 2020, 67, 3828 -3838.

AMA Style

Yan-Peng Chen, Kea-Tiong Tang. A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference. IEEE Transactions on Circuits and Systems I: Regular Papers. 2020; 67 (11):3828-3838.

Chicago/Turabian Style

Yan-Peng Chen; Kea-Tiong Tang. 2020. "A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 11: 3828-3838.

Journal article
Published: 14 July 2020 in IEEE Journal of Solid-State Circuits
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Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high-precision operations, large cell array area overhead, and limited compatibility with many input and weight configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing multibit PS accumulation to increase read accuracy and reduce area overhead; 2) column-based place-value-grouped weight mapping and a serial-bit input (SBIN) mapping scheme to facilitate reconfiguration and increase array efficiency under various input and weight configurations; 3) a self-reference multilevel reader (SRMLR) to reduce read-out energy and achieve a sensing margin 2x that of the mid-point reference scheme; and 4) an input-aware bitline voltage compensation scheme to ensure successful read operations across various input-weight patterns. A 4-Kb configurable 6T-SRAM CIM unit-macro was fabricated using a 55-nm CMOS process with foundry 6T-SRAM cells. The resulting macro achieved access times of 3.5 ns per cycle (pipeline) and energy efficiency of 0.6-40.2 TOPS/W under binary to 8-b input/8-b weight precision.

ACS Style

Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; Sih-Han Li; Chih-I Wu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Meng-Fan Chang. A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits 2020, 55, 2790 -2801.

AMA Style

Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits. 2020; 55 (10):2790-2801.

Chicago/Turabian Style

Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; Sih-Han Li; Chih-I Wu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Meng-Fan Chang. 2020. "A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors." IEEE Journal of Solid-State Circuits 55, no. 10: 2790-2801.

Journal article
Published: 04 May 2020 in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
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ACS Style

Wei-Chen Wei; Chuan-Jia Jhang; Yi-Ren Chen; Cheng-Xin Xue; Syuan-Hao Sie; Jye-Luen Lee; Hao-Wen Kuo; Chih-Cheng Lu; Meng-Fan Chang; Kea-Tiong Tang. A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2020, 6, 45 -52.

AMA Style

Wei-Chen Wei, Chuan-Jia Jhang, Yi-Ren Chen, Cheng-Xin Xue, Syuan-Hao Sie, Jye-Luen Lee, Hao-Wen Kuo, Chih-Cheng Lu, Meng-Fan Chang, Kea-Tiong Tang. A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 2020; 6 (1):45-52.

Chicago/Turabian Style

Wei-Chen Wei; Chuan-Jia Jhang; Yi-Ren Chen; Cheng-Xin Xue; Syuan-Hao Sie; Jye-Luen Lee; Hao-Wen Kuo; Chih-Cheng Lu; Meng-Fan Chang; Kea-Tiong Tang. 2020. "A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory." IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6, no. 1: 45-52.

Journal article
Published: 27 November 2019 in IEEE Journal of Solid-State Circuits
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Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even-odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two's complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global-local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 x 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5-45.36 TOPS/W under 5-b MACV output.

ACS Style

Xin Si; Rui Liu; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits 2019, 55, 189 -202.

AMA Style

Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits. 2019; 55 (1):189-202.

Chicago/Turabian Style

Xin Si; Rui Liu; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun. 2019. "A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors." IEEE Journal of Solid-State Circuits 55, no. 1: 189-202.

Journal article
Published: 22 November 2019 in IEEE Journal of Solid-State Circuits
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Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area-latency-energy tradeoff for multibit MAC operations, pattern-dependent degradation in signal margin, and small read margin. To overcome these challenges, this article proposes the following: 1) a serial-input non-weighted product (SINWP) structure; 2) a down-scaling weighted current translator (DSWCT) and positive-negative current-subtractor (PN-ISUB); 3) a current-aware bitline clamper (CABLC) scheme; and 4) a triple-margin small-offset current-mode sense amplifier (TMCSA). A 55-nm 1-Mb ReRAM-CIM macro was fabricated to demonstrate the MAC operation of 2-b-input, 3-b-weight with 4-b-out. This nvCIM macro achieved TMAC= 14.6 ns at 4-b-out with peak energy efficiency of 53.17 TOPS/W.

ACS Style

Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong-Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; Meng-Fan Chang; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Jing-Hong Wang; Wei-Chen Wei; Tsung-Yuan Huang. Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits 2019, 55, 203 -215.

AMA Style

Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Hao Chen, Meng-Fan Chang, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang. Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE Journal of Solid-State Circuits. 2019; 55 (1):203-215.

Chicago/Turabian Style

Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong-Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; Meng-Fan Chang; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Jing-Hong Wang; Wei-Chen Wei; Tsung-Yuan Huang. 2019. "Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors." IEEE Journal of Solid-State Circuits 55, no. 1: 203-215.

Journal article
Published: 11 September 2019 in Micromachines
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Metal-oxide (MOX) gas sensors are widely used for gas concentration estimation and gas identification due to their low cost, high sensitivity, and stability. However, MOX sensors have low selectivity to different gases, which leads to the problem of classification for mixtures and pure gases. In this study, a square wave was applied as the heater waveform to generate a dynamic response on the sensor. The information of the dynamic response, which includes different characteristics for different gases due to temperature changes, enhanced the selectivity of the MOX sensor. Moreover, a polynomial interaction term mixture model with a dynamic response is proposed to predict the concentration of the binary mixtures and pure gases. The proposed method improved the classification accuracy to 100%. Moreover, the relative error of quantification decreased to 1.4% for pure gases and 13.0% for mixtures.

ACS Style

Wei-Chih Wen; Ting-I Chou; Kea-Tiong Tang. A Gas Mixture Prediction Model Based on the Dynamic Response of a Metal-Oxide Sensor. Micromachines 2019, 10, 598 .

AMA Style

Wei-Chih Wen, Ting-I Chou, Kea-Tiong Tang. A Gas Mixture Prediction Model Based on the Dynamic Response of a Metal-Oxide Sensor. Micromachines. 2019; 10 (9):598.

Chicago/Turabian Style

Wei-Chih Wen; Ting-I Chou; Kea-Tiong Tang. 2019. "A Gas Mixture Prediction Model Based on the Dynamic Response of a Metal-Oxide Sensor." Micromachines 10, no. 9: 598.

Journal article
Published: 06 August 2019 in IEEE Sensors Letters
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Ketamine severely endangers health and dwelling quality. In Taiwan, one of the common methods of taking ketamine is by smoking ketamine cigarettes. By heating up ketamine cigarettes, it produces an odor that smells similar to burning plastic. There are no effective and convenient methods for immediately detecting and identifying the smell of ketamine cigarettes. Therefore, this research proposed to develop an electronic nose system to identify the gas of ketamine cigarettes. In this study, standard operating procedures were established for collecting ketamine gas and ketamine cigarette gas at constant flow to quantitatively collect those gas samples least affected by environmental factors. After injecting the gas samples, the variation signal of sensor array was noted. By feature extraction and dimensionality reduction algorithms, the complexity of data decreased. The classification results were also analyzed through linear regression and classification algorithms, and the classification accuracy was up to 95.92%.

ACS Style

Cheng-Chun Wu; Shih-Wen Chiu; Kea-Tiong Tang. An Electronic Nose System for Rapid Detection of Ketamine Smoke. IEEE Sensors Letters 2019, 3, 1 -4.

AMA Style

Cheng-Chun Wu, Shih-Wen Chiu, Kea-Tiong Tang. An Electronic Nose System for Rapid Detection of Ketamine Smoke. IEEE Sensors Letters. 2019; 3 (8):1-4.

Chicago/Turabian Style

Cheng-Chun Wu; Shih-Wen Chiu; Kea-Tiong Tang. 2019. "An Electronic Nose System for Rapid Detection of Ketamine Smoke." IEEE Sensors Letters 3, no. 8: 1-4.

Journal article
Published: 24 April 2019 in Micromachines
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The objective of this research was to develop a surface-acoustic-wave (SAW) sensor of cigarette smoke to prevent tobacco hazards and to detect cigarette smoke in real time through the adsorption of an ambient tobacco marker. The SAW sensor was coated with oxidized hollow mesoporous carbon nanospheres (O-HMC) as a sensing material of a new type, which replaced a polymer. O-HMC were fabricated using nitric acid to form carboxyl groups on carbon frameworks. The modified conditions of O-HMC were analyzed with Scanning Electron Microscopy (SEM), Fourier transform infrared spectrometry (FTIR), and X-ray diffraction (XRD). The appropriately modified O-HMC are more sensitive than polyacrylic acid and hollow mesoporous carbon nanospheres (PAA-HMC), which is proven by normalization. This increases the sensitivity of a standard tobacco marker (3-ethenylpyridine, 3-EP) from 37.8 to 51.2 Hz/ppm and prevents the drawbacks of a polymer-based sensing material. On filtering particles above 1 μm and using tar to prevent tar adhesion, the SAW sensor detects cigarette smoke with sufficient sensitivity and satisfactory repeatability. Tests, showing satisfactory selectivity to the cigarette smoke marker (3-EP) with interfering gases CH4, CO, and CO2, show that CO and CO2 have a negligible role during the detection of cigarette smoke.

ACS Style

Chi-Yung Cheng; Shih-Shien Huang; Chia-Min Yang; Kea-Tiong Tang; Da-Jeng Yao. Detection of Cigarette Smoke Using a Surface-Acoustic-Wave Gas Sensor with Non-Polymer-Based Oxidized Hollow Mesoporous Carbon Nanospheres. Micromachines 2019, 10, 276 .

AMA Style

Chi-Yung Cheng, Shih-Shien Huang, Chia-Min Yang, Kea-Tiong Tang, Da-Jeng Yao. Detection of Cigarette Smoke Using a Surface-Acoustic-Wave Gas Sensor with Non-Polymer-Based Oxidized Hollow Mesoporous Carbon Nanospheres. Micromachines. 2019; 10 (4):276.

Chicago/Turabian Style

Chi-Yung Cheng; Shih-Shien Huang; Chia-Min Yang; Kea-Tiong Tang; Da-Jeng Yao. 2019. "Detection of Cigarette Smoke Using a Surface-Acoustic-Wave Gas Sensor with Non-Polymer-Based Oxidized Hollow Mesoporous Carbon Nanospheres." Micromachines 10, no. 4: 276.

Conference paper
Published: 01 October 2018 in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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A high resolution and low power fully differential 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this work aiming at neural signal data acquisition. By utilizing surplus energy restored by MSB-split capacitors of alternative switching structure both in conversion phase and reset phase, the proposed charge average and skip switching algorithm achieves superior DAC switching energy efficiency without the requirement of an external Vcm reference. Implemented in 180nm CMOS process, the proposed chip occupied a 0.0564-mm 2 core area. Operating at 320-kS/s sampling rate with 0.65-V supply voltage, it achieved an ENOB of 9.66-bit and FoM of 6.26 fJ/conv.-step. The measured DNL and INL results are within 0.29 LSB and 0.38 LSB, respectively.

ACS Style

Yi-Han Ou-Yang; Cheng-Chun Wu; Kea-Tiong Tang. A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018, 98 -101.

AMA Style

Yi-Han Ou-Yang, Cheng-Chun Wu, Kea-Tiong Tang. A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). 2018; ():98-101.

Chicago/Turabian Style

Yi-Han Ou-Yang; Cheng-Chun Wu; Kea-Tiong Tang. 2018. "A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm." 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , no. : 98-101.

Journal article
Published: 27 September 2018 in Sensors
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Electronic nose (E-nose) systems have become popular in food and fruit quality evaluation because of their rapid and repeatable availability and robustness. In this paper, we propose an E-nose system that has potential as a non-destructive system for monitoring variation in the volatile organic compounds produced by fruit during the maturing process. In addition to the E-nose system, we also propose a camera system to monitor the peel color of fruit as another feature for identification. By incorporating E-nose and camera systems together, we propose a non-destructive solution for fruit maturity monitoring. The dual E-nose/camera system presents the best Fisher class separability measure and shows a perfect classification of the four maturity stages of a banana: Unripe, half-ripe, fully ripe, and overripe.

ACS Style

Li-Ying Chen; Cheng-Chun Wu; Ting-I. Chou; Shih-Wen Chiu; Kea-Tiong Tang. Development of a Dual MOS Electronic Nose/Camera System for Improving Fruit Ripeness Classification. Sensors 2018, 18, 3256 .

AMA Style

Li-Ying Chen, Cheng-Chun Wu, Ting-I. Chou, Shih-Wen Chiu, Kea-Tiong Tang. Development of a Dual MOS Electronic Nose/Camera System for Improving Fruit Ripeness Classification. Sensors. 2018; 18 (10):3256.

Chicago/Turabian Style

Li-Ying Chen; Cheng-Chun Wu; Ting-I. Chou; Shih-Wen Chiu; Kea-Tiong Tang. 2018. "Development of a Dual MOS Electronic Nose/Camera System for Improving Fruit Ripeness Classification." Sensors 18, no. 10: 3256.

Conference paper
Published: 26 October 2017 in Computer Vision
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Portable or biomedical applications typically require signal processing, learning, and classification in conditions involving limited area and power consumption. Analog implementations of learning algorithms can satisfy these requirements and are thus attracting increasing attention. Probabilistic spiking neural network (PSNN) is a hardware friendly algorithm that is relax in weight resolution requirements and insensitive to noise and VLSI process variation. In this study, the probabilistic spiking neural network was implemented using analog very-large-scale integration (VLSI) to verify their hardware compatibility. The circuit was fabricated using 0.18 μm CMOS technology. The power consumption of the chip was less than 10 μW with a 1 V supply and the core area of chip was 0.43 mm2. The chip can classify the electronic nose data with 92.3% accuracy and classify the electrocardiography data with 100% accuracy. The low power and high learning performance features make the chip suitable for portable or biomedical applications.

ACS Style

Hung-Yi Hsieh; Pin-Yi Li; Kea-Tiong Tang. An Analog Probabilistic Spiking Neural Network with On-Chip Learning. Computer Vision 2017, 777 -785.

AMA Style

Hung-Yi Hsieh, Pin-Yi Li, Kea-Tiong Tang. An Analog Probabilistic Spiking Neural Network with On-Chip Learning. Computer Vision. 2017; ():777-785.

Chicago/Turabian Style

Hung-Yi Hsieh; Pin-Yi Li; Kea-Tiong Tang. 2017. "An Analog Probabilistic Spiking Neural Network with On-Chip Learning." Computer Vision , no. : 777-785.