The deployment of photonic integrated circuits (PICs) necessitates an integration platform that is scalable, high-throughput, cost-effective, and power-efficient. Here we present a monolithic InP on SOI platform to synergize the advantages of two mainstream photonic integration platforms: Si photonics and InP photonics. This monolithic InP/SOI platform is realized through the selective growth of both InP sub-micron wires and large dimension InP membranes on industry-standard (001)-oriented silicon-on-insulator (SOI) wafers. The epitaxial InP is in-plane, dislocation-free, site-controlled, intimately positioned with the Si device layer, and placed right on top of the buried oxide layer to form “InP-on-insulator”. These attributes allow for the realization of various photonic functionalities using the epitaxial InP, with efficient light interfacing between the III–V devices and the Si-based waveguides. We exemplify the potential of this InP/SOI platform for integrated photonics through the demonstration of lasers with different cavity designs including subwavelength wires, square cavities, and micro-disks. Our results here mark a critical step forward towards fully-integrated Si-based PICs.

Realizing efficient on-chip light sources has long been the “holy-grail” for Si-photonics research. Several important breakthroughs were made in this field in the past few years. In this article, we review the most recent advances in light sources integrated onto mainstream Si platforms and discuss four different integration technologies: Group IV light sources on Si, heterogeneous integration of III–V light sources on Si, blanket heteroepitaxy of III–V light sources on Si, and selective heteroepitaxy of III–V light sources on Si. We start with briefly introducing the basic concepts of each technology and then focus on the recent progress via presenting the most representative device demonstrations. Finally, we discuss the research challenges and opportunities associated with each technology.

Integrating light emission and detection functionalities using efficient III-V materials on Si wafers is highly desirable for Si-based photonic integrated circuits. To fulfill the need of high-performance photodetectors (PDs) monolithically integrated on Si for Si photonics, we demonstrate III-V PDs directly grown on a InP/Si-on-insulator (SOI) platform parallel to the Si device layer in a variety of device dimensions. Device characteristics including a 3 dB bandwidth beyond 40 GHz, open eye diagrams at 40 Gb/s, a dark current of 0.55 nA, a responsivity of 0.3 A/W at 1550 nm, and 0.8 A/W at 1310 nm together with a 410 nm operation wavelength span from 1240 nm to 1650 nm are achieved. We further simulate the feasibility of interfacing the III-V PDs with the Si waveguide by designing waveguide-coupled PDs with butt coupling schemes. These results point to a practical solution for the monolithic integration of III-V active components and Si-based passive devices on a InP/SOI platform in the future.

Seamlessly integrating III-V active devices with Si passive components in a monolithic manner is the key for fully integrated Si photonics. In this article, we demonstrate high-performance III-V photodetectors directly grown on industry-standard (001)-oriented silicon-on-insulator (SOI) wafers and intimately coupled with Si waveguides. The Si-waveguide-coupled III-V photodetectors feature a low dark current of 60 pA corresponding to a current density of 0.002 A / c m 2 , a large photocurrent exceeding 1 mA, responsivities of 0.4 A/W at 1.3 µm and 0.2 A/W at 1.5 µm, and a large detection wavelength range over the entire telecom band. High-speed measurements reveal a 3 dB bandwidth over 52 GHz and a data communication rate of 112 Gb/s with four-level pulse-amplitude modulation and 100 Gb/s with on–off keying. The monolithic integration scheme demonstrated for III-V photodetectors in this work is also applicable to future seamless integration of III-V lasers on the Si-photonics platform.

Efficient on-chip laser sources of Si photonics can be built from direct epitaxy of dislocation-free III–V alloys on industrial-standard (001) Si wafers. Here, we report on selective lateral epitaxy of InP on patterned (001) silicon-on-insulators (SOIs) by metal organic chemical vapor deposition. Based on the conventional “aspect ratio trapping” approach, we created undercut patterns to alter the growth front to the lateral direction. Growth of InP inside the nano-scale SOI trenches results in dislocation-free InP crystals right atop the buried oxide layer. The intimate placement of the InP crystals with the Si device layer points to the development of dislocation-free nano-ridges for integration of efficient III–V light emitters with Si-based photonic components on SOI.

Epitaxially integrating III-V lasers with Si-photonics is the key for compact, efficient, and scalable photonic integrated circuits (PICs). Here we present an investigation of a path forward in integrating III-V functionalities on industry-standard silicon-on-insulator (SOI) platforms using selective area hetero-epitaxy. Based on our recently developed methods of selectively growing device quality InP on (001)-oriented SOI wafers, we demonstrated InP stripes and segments, with dimensions varying from a few hundred nanometers to a few micrometers. The flexible epitaxy of InP on SOI together with the unique “bufferless” trait will enable efficient light interfacing with Si-based photonic devices using either evanescent or butt coupling schemes. We simulated the possibility of employing the micrometer-scale InP on insulator to realize electrically driven lasers and found that the metal induced optical loss is negligible when the InP dimension exceeds 4.0 μm. The potential of utilizing this selective area growth method to realize fully integrated Si-photonics is illustrated.