Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact and demonstrates that ECCs shorten the lifetime of STT-RAM cache lines by more than 50 percent due to ECCs high write activity. Then, we propose the Floating-ECC architecture for increasing the lifetime of the STT-RAM caches. The main idea is to evenly distribute the ECC write activity over all bits of cache lines by periodically relocating the ECC bits inside the cache lines. The simulation results for the most conventional ECC scheme, i.e., interleaved Single Error Correction-Double Error Detection (SEC-DED), show that Floating-ECC increases the lifetime of L2 and L3 caches by more than 318 percent and 254 percent, respectively.

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, $Spin$ - $Transfer\; Torque\; Magnetic\; RAM$ (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to $retention\; failure$ , $write\; failure$ , and $read\; disturbance$ threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly increased in higher temperature, which further affects the reliability of STT-MRAM-based cache memories. The major source of heat generation and temperature increase in STT-MRAM cache memories is write operations, which are managed by cache $replacement\; policy$ . To the best of our knowledge, none of previous studies have attempted to mitigate heat generation and high temperature of STT-MRAM cache memories using replacement policy. In this paper, we first analyze the cache behavior in conventional $Least$ - $Recently\; Used$ (LRU) replacement policy and demonstrate that the majority of consecutive write operations (more than 66 percent) are committed to adjacent cache blocks. These adjacent write operations cause accumulated heat and increased temperature, which significantly increase the cache error rate. To eliminate heat accumulation and the adjacency of consecutive writes, we propose a cache replacement policy, named $Thermal$ - $Aware\; Least$ - $Recently\; Written$ (TA-LRW), to smoothly distribute the generated heat by conducting consecutive write operations in distant cache blocks. TA-LRW guarantees the distance of at least three blocks for each two consecutive write operations in an 8-way associative cache. This distant write scheme reduces the temperature-induced error rate by 94.8 percent, on average, compared with the conventional LRU policy, which results in 6.9x reduction in cache error rate. The implementation cost and complexity of TA-LRW is as low as $First$ - $In,\; First$ - $Out$ (FIFO) policy while providing a near-LRU performance, having the advantages of both replacement policies. The significantly reduced error rate is achieved by imposing only 2.3 percent performance overhead compared with the LRU policy.

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new doorto respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches. High probability of write error due to stochastic switching is a major problem in STT-RAMs. Conventional Error-Correcting Codes (ECCs) impose significant area and energy consumption overheads to protect STT-RAM caches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A²PT) to efficiently protect the STT-RAM caches. A²PT benefits from error rate asymmetry of STT-RAM write operations to provide the required level of cache protection with significantly lower overheads. Compared with the conventional ECC configuration, the evaluation results show that A²PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection. Moreover, A²PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving in write energy consumption.

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To this end, instead of protecting all cache lines using strong ECCs, AWARE employs a simple ECC that guarantees a given reliability level for the majority of writes. Meanwhile, when a data block with high error rate is written, one way in the target set is adaptively configured to store the check bits of a strong ECC for this block. The evaluation results show that, compared with conventional ECCs, AWARE reduces the ECC area by about 81.2% and the cache energy consumption by about 9.5%. These reductions are achieved by imposing less than 1% performance overhead and without compromising the reliability.

Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In this paper, we propose a system-level framework for reliability exploration and characterization of errors’ behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the intercorrelation of the error types including RF, read disturbance, and write failure as well as the dependency of error rates to workloads’ behavior and process variations (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by PVs in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multiprogrammed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0×for different workloads. A further 6.5× vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.