Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis^1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures^4,5, as well as hetero-2D layers with different carrier types^6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe₂ (refs. ^9–17) and MoS₂ (refs. ^11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS₂, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS₂ can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm² V⁻¹ s⁻¹, on/off ratios reaching 10⁶ and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide-semiconductor field effect transistors (MOS-FETs) would be the three dimensionalized version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During the past decades, the width of fin (W $${}_{{\rm{fin}}}$$fin ) in FinFETs has shrunk from about 150 nm to a few nanometers. However, W $${}_{{\rm{fin}}}$$fin seems to have been levelling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting a template-growth method, different types of mono-layered two-dimensional crystals are isolated in a vertical manner. Based on this, FinFETs with one atomic layer fin are obtained, with on/off ratios reaching $$\sim\!\! 10^{7}$$~107 . Our findings push the FinFET to the sub 1 nm fin-width limit, and may shed light on the next generation nanoelectronics for higher integration and lower power consumption.

Recently, the emerging conceptual valley-related devices have attracted much attention due to the progress on generating, controlling, and detecting the valley degree of freedom in the transition metal dichalcogenide (TMD) monolayers. In general, it is known that achieving valley degree of freedom with long valley lifetime is crucial in the implementation of valleytronic devices. Here, we provide a brief introduction of the basic understandings of valley degree of freedom. We as well review the recent experimental advancement in the modulation of valley degree of freedom. The strategies include optical/magnetic/electric field tuning, moiré patterns, plasmonic metasurface, defects and strain engineering. In addition, we summarize the corresponding mechanisms, which can help to obtain large degree of polarization and long valley lifetimes in monolayer TMDs. Based on these methods, two-dimensional valley-optoelectronic systems based on TMD heterostructures can be constructed, providing opportunities for such as the new paradigm in data processing and transmission. Challenges and perspectives on the development of valleytronics are highlighted as well.

Ferroelectricity, one of the keys to realize non‐volatile memories owing to the remanent electric polarization, is an emerging phenomenon in the 2D limit. Yet the demonstrations of van der Waals (vdW) memories using 2D ferroelectric materials as an ingredient are very limited. Especially, gate‐tunable ferroelectric vdW memristive device, which holds promises in future multi‐bit data storage applications, remains challenging. Here, a gate‐programmable multi‐state memory is shown by vertically assembling graphite, CuInP₂S₆, and MoS₂ layers into a metal(M)‐ferroelectric(FE)‐semiconductor(S) architecture. The resulted devices seamlessly integrate the functionality of both FE‐memristor (with ON–OFF ratios exceeding 10⁵ and long‐term retention) and metal‐oxide‐semiconductor field effect transistor (MOS‐FET). Thus, it yields a prototype of gate tunable giant electroresistance with multi‐levelled ON‐states in the FE‐memristor in the vertical vdW assembly. First‐principles calculations further reveal that such behaviors originate from the specific band alignment between the FE‐S interface. Our findings pave the way for the engineering of ferroelectricity‐mediated memories in future implementations of 2D nanoelectronics.

The realization of graphene gapped states with large on/off ratios over wide doping ranges remains challenging. Here, we investigate heterostructures based on Bernal-stacked bilayer graphene (BLG) atop few-layered CrOCl, exhibiting an over-1-GΩ-resistance insulating state in a widely accessible gate voltage range. The insulating state could be switched into a metallic state with an on/off ratio up to 10⁷by applying an in-plane electric field, heating, or gating. We tentatively associate the observed behavior to the formation of a surface state in CrOCl under vertical electric fields, promoting electron–electron (e–e) interactions in BLG via long-range Coulomb coupling. Consequently, at the charge neutrality point, a crossover from single particle insulating behavior to an unconventional correlated insulator is enabled, below an onset temperature. We demonstrate the application of the insulating state for the realization of a logic inverter operating at low temperatures. Our findings pave the way for future engineering of quantum electronic states based on interfacial charge coupling.