This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm ² .

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.

A 9.1ENOB 200 MS/s asynchronous SAR analog-to-digital converter (ADC) dealing with image sensing signals is presented in this paper. The proposed ADC, designed in 55-nm CMOS process technology, can work in both single-ended and differential modes. To guarantee the ADC linearity, a symmetrical switching method is adopted. To ensure the reference accuracy when the ADC is in operation, a 1.2-V on-chip quick-response LDO, which works under a 2.5-V supply, is also integrated. To overcome the need for a clock-generation circuit and avoid a high-speed interface circuit design, asynchronous clock logic is chosen. In addition, the comparison cycle is adjusted dynamically to guarantee the DAC settling and improve the ADC throughput. In the differential operation mode, the proposed SAR ADC exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB and a peak spurious-free-dynamic-range (SFDR) of 68 dB with the Nyquist input, at a 200-MS/s output rate. The ADC consumes 2.74 mW, resulting in a figure-of-merit (FOM) of 25-fJ/conversion-step. Meanwhile, in the single-ended mode, the SNDR and SFDR of the ADC are 53and 64 dB, respectively. And the power consumption is 2.25 mW, resulting in an FOM of 31-fJ/conversion-step. The area of the proposed ADC is 280 × 380 μm ₂ and the ADC core occupies an active area of only 140 × 250 μm ² .

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- $\mu $ m CMOS process, the prototype occupies 1.01 mm $^{2}$ . On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.

Negative capacitance FET (NCFET) has become a research topic of interest in recent years due to its interesting properties. It has the ability to retain the polarization state even in the absence of electric field. By virtue of this ability, it can be designed as a nonvolatile memory. NCFET can also be configured as a steep-slope switch and thereby providing energy efficiency while used in digital designs. However, the benefits offered by NCFETs for analog circuit domain has not well reported. In this paper, we analyze the impact of body effect on an NCFET-based bootstrapped switch and illustrate that the linearity of NCFET-based switch can be improved resulting from the internal amplification of the employed NCFET. When designed at 0.6-V supply (V _dd ), results show that the variation of the on resistance of the bootstrapped switch is about 67 Ω during the sampling period, which is one-third smaller than the MOSFET-based switch. As a result, the sampling linearity is improved and the distortion at the output can be decreased. On condition that the Nyquist input frequency is 10 MHz, the proposed NCFETbased bootstrapped switch succeeds in improving the total harmonic distortion performance by 16.7 dB, compared with that of a conventional MOSFET-based bootstrapped switch.