This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm². The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mV_pp output. The amplifier can provide a noise level of 1.18 μV_rms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μV_rms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm². According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset.