The monolithic integration of III-V compound semiconductor devices with silicon presents physical and technological challenges, linked to the creation of defects during the deposition process. Herein, a new defect elimination strategy in highly mismatched heteroepitaxy is demonstrated to achieve a ultra-low dislocation density, epi-ready Ge/Si virtual substrate on a wafer scale, using a highly scalable process. Dislocations are eliminated from the epilayer through dislocation-selective electrochemical deep etching followed by thermal annealing, which creates nanovoids that attract dislocations, facilitating their subsequent annihilation. The averaged dislocation density is reduced by over three orders of magnitude, from ~10⁸ cm⁻² to a lower-limit of ~10⁴ cm⁻² for 1.5 µm thick Ge layer. The optical properties indicate a strong enhancement of luminescence efficiency in GaAs grown on this virtual substrate. Collectively, this work demonstrates the promise for transfer of this technology to industrial-scale production of integrated photonic and optoelectronic devices on Si platforms in a cost-effective way.

We have performed a detailed characterization study of electrochemically etched p-type GaAs in a hydrofluoric acid-based electrolyte. The samples were investigated and characterized through cathodoluminescence (CL), X-ray diffraction (XRD), energy-dispersive X-ray spectroscopy (EDX), and X-ray photoelectron spectroscopy (XPS). It was found that after electrochemical etching, the porous layer showed a major decrease in the CL intensity and a change in chemical composition and in the crystalline phase. Contrary to previous reports on p-GaAs porosification, which stated that the formed layer is composed of porous GaAs, we report evidence that the porous layer is in fact mainly constituted of porous As2O3. Finally, a qualitative model is proposed to explain the porous As2O3 layer formation on p-GaAs substrate.

A perfectly compliant substrate would allow the monolithic integration of high-quality semiconductor materials such as Ge and III-V on Silicon (Si) substrate, enabling novel functionalities on the well-established low-cost Si technology platform. Here, we demonstrate a compliant Si substrate allowing defect-free epitaxial growth of lattice mismatched materials. The method is based on the deep patterning of the Si substrate to form micrometer-scale pillars and subsequent electrochemical porosification. The investigation of the epitaxial Ge crystalline quality by X-ray diffraction, transmission electron microscopy and etch-pits counting demonstrates the full elastic relaxation of defect-free microcrystals. The achievement of dislocation free heteroepitaxy relies on the interplay between elastic deformation of the porous micropillars, set under stress by the lattice mismatch between Ge and Si, and on the diffusion of Ge into the mesoporous patterned substrate attenuating the mismatch strain at the Ge/Si interface.

Porous germanium (PGe) nanostructures attract a lot of attention for various emerging applications due to their unique properties. Consequently, there is an increasing need for the development of low‐cost synthesis routes that are compatible with large‐scale production. Bipolar electrochemical etching (BEE) is a widely used solution for producing porous Ge layers. However, the lack of controllable production of large‐scale uniform PGe layers is the limiting factor for mainstream applications. Large‐scale homogeneous PGe layers formation is demonstrated by improving the BEE process. The PGe structures demonstrate excellent homogeneity in thickness and porosity, with a relative variation of below 2% across the 100 mm wafer. Furthermore, this process enables accurate tuning of the PGe's physical properties through variation of the etching parameters. PGe structures with porosity ranging from 40% to 80% and an adjustable thickness, while preserving low surface roughness are demonstrated, giving access to a large variety of PGe nanostructures for a wide range of applications. Ellipsometry and X‐ray reflectivity are employed to measure the porosity and thickness of PGe layers, providing fast and non‐destructive methods of characterization. These findings lay the groundwork for the large‐scale production of high‐quality PGe layers with on‐demand characteristics.

The Porous germanium Efficient Epitaxial LayEr Release (PEELER) process is introduced allowing the fabrication of wafer scale detachable monocrystalline Ge nanomembranes compatible with III–V material growth on porous Ge and substrate reuse.