In this paper, we propose a lightweight U-net architecture neural network model based on Dark Channel Prior (DCP) for efficient haze (fog) removal with a single input. The existing DCP requires high computational complexity in its operation. These computations are challenging to accelerate, and the problem is exacerbated when dealing with high-resolution images (videos), making it very difficult to apply to general-purpose applications. Our proposed model addresses this issue by employing a two-stage neural network structure, replacing the computationally complex operations of the conventional DCP with easily accelerated convolution operations to achieve high-quality fog removal. Furthermore, our proposed model is designed with an intuitive structure using a relatively small number of parameters (2M), utilizing resources efficiently. These features demonstrate the effectiveness and efficiency of the proposed model for fog removal. The experimental results show that the proposed neural network model achieves an average Peak Signal-to-Noise Ratio (PSNR) of 26.65 dB and a Structural Similarity Index Measure (SSIM) of 0.88, indicating an improvement in the average PSNR of 11.5 dB and in SSIM of 0.22 compared to the conventional DCP. This shows that the proposed neural network achieves comparable results to CNN-based neural networks that have achieved SOTA-class performance, despite its intuitive structure with a relatively small number of parameters.

In this paper, we propose an effective algorithm of pipelined dividers for double-precision floating-point numbers. This reduces the latency of the previous pipelined dividers without increasing the lookup table size. The experimental results show that the proposed divider reduces the overall latency up to 16% compared to the previous divider.

Crowd-related disasters in dense public spaces unfold into hazardous situations within seconds, repeatedly demonstrating that reactive response alone is insufficient to minimize damage. This reality has intensified the need for monitoring systems that can proactively forecast congestion before it reaches a critical level. Digital twin platforms address this need by providing an operational substrate that represents crowd states on a unified bird’s-eye-view (BEV) grid, on which a predictive module can forecast where congestion will emerge. However, conventional AI-based single-stage dense prediction models are intrinsically ill-suited to this role: although crowd congestion is sparse in both space and time, these models apply uniform high-resolution computation across the entire BEV domain, wasting computation and biasing optimization toward dominant background regions. In this paper, we propose a two-stage coarse-to-fine framework that operates as the predictive module of the digital twin and explicitly exploits the spatio-temporal sparsity of crowd congestion. The first stage, CoarseSTFormer, performs efficient global screening on a low-resolution BEV input to coarsely identify a set of density-critical candidate regions. The second stage, SparseQueryDecoder, selectively reconstructs high-resolution responses only on the identified candidates, rather than uniformly upsampling the entire BEV grid. In simulation environments with up to 20,000 pedestrian agents, the proposed framework matches the strongest dense baseline in reconstruction quality while delivering the most balanced variance profile across grid scales. At inference, it further reduces GPU energy consumption by $1.9\times$ to $5.0\times$ and computational cost (FLOPs) by $3.8\times$ to $54\times$, demonstrating its practicality as a resource-efficient predictive module that satisfies both accuracy and efficiency.

With the growing interest in digital twin technology, there has been a rise in efforts to apply technology in diverse fields. The digital twin can provide opportunities for humans to benefit in both industrial and daily life. We propose a digital twin platform, MirrorLake, designed to support the effective construction and utilization of digital twins by providing core functionalities aligned with the unique characteristics of digital twins. We proposed the digital twin resource management system to handle the representative components of the digital twin that emerged from our in-depth research analysis. We also implemented a synchronization engine and its ecosystem that supports high-volume and bidirectional synchronization between the real and virtual worlds. The engine also supports synchronization between the components of the digital twin by accommodating heterogeneity and linking real-time data. We demonstrated the utility of MirrorLake through three real-world applications in the city environment, smart office, and public safety, highlighting its potential to facilitate digital transformation in various industries.

In this paper, we propose a load balancing algorithm that accelerates ray tracing effectively and simply manner. The algorithm was developed in a hybrid system consisting of a CPU and hardware dedicated to ray tracing. Tree-building is processed on the CPU, and rendering is executed by the ray tracing-dedicated hardware. Because these components operate independently of each other, the final performance in terms of frames per second (FPS) is determined based on the time spent on tree-building or rendering, whichever process takes longer. This characteristic of a hybrid system is reflected in the developed algorithm, which dynamically adjusts tree-build parameters at every frame, thereby minimizing the interval between tree-building and rendering times. These effects ultimately increase FPS performance. Experiments at a resolution of 1920 × 1080 involving various dynamic scenes indicated that FPS performance improved by an average of 75.3% when the proposed algorithm was used.

In this paper, we propose a multi-chip architecture based on parallel frame rendering suitable for real-time ray tracing in dynamic scenes. In multi-chip architecture with the commonly used screen partitioning method, the acceleration structure data, such as a tree, updated in a dynamic scene must be transmitted to each chip. In the proposed frame division method, a tree build and ray tracing are performed on the same chip, and each frame is allocated to a predesignated multi-chip. Thus, the proposed method can achieve scalable performance improvement not only of ray tracing but also of a tree build. We implemented a multi-chip architecture on three field-programmable gate array (FPGA) boards and built 12 ray-tracing cores in the FPGA chip of each board. This configuration means that the inter-chip operates using the frame division method, while the inner chip operates using the screen partitioning method. The results of experiments showed that the proposed multi-chip architecture improved frames per second (FPS) performance by an average of 2.83 times compared to a single-chip architecture.