Chaotic systems have been applied in many applications involving instrumentation and measurements, such as in sensors and control systems, due to their pseudo-random proprieties. However, reproducing chaos in digital systems is challenging because of the dynamical degradation of chaotic digital systems and, consequently, their intrinsic periodic orbits. Many techniques have been employed to guarantee a sufficiently large period, making them suitable for such applications. Nevertheless, few papers pay attention to the effects of using different numerical representations on chaos degradation and, at the same time, keeping key design parameters, such as few logical resources and power consumption. Thus, this paper aims to provide a new hardware architecture for a chaos-based PRNG using the Half-Unit-Biased (HUB) format for fixed-point numbers by bi-coupling the tent map in conjunction with the Bernoulli map, causing a significant impact on its logical resources and performance. Results show that the HUB format is more effective than the standard fixed-point numerical representation and that the proposed approach is chaotic, with pseudo-randomness.

It is known, that coherent chaotic communication systems are more vulnerable to noise in the transmission channel than conventional communications. Among the methods of noise impact reduction, such as extended symbol length and various digital filtering algorithms, the optimization of the synchronization coefficient may appear as a very efficient and simple straightforward approach. However, finding the optimal coefficient for the synchronization of two chaotic oscillators is a challenging task due to the high sensitivity of chaos to any disturbances. In this paper, we propose an algorithm for finding the optimal synchronization parameter K_opt for a coherent chaos-based communication system affected by various noises with different signal-to-noise ratios (SNR). It is shown, that under certain conditions, optimal $K$ provides the lowest possible bit error rate (BER) during the transmission. In addition, we show that various metrics applied to the message demodulation task propose different noise immunity to the overall system. For the experimental part of the study, we simulated and physically prototyped two chaotic communication systems based on well-known Rossler and Lorenz chaotic oscillators. The microcontroller-based prototype of a chaotic communication system was developed to investigate the influence of noise in the real transmission channel. The experimental results obtained using the designed hardware testbench are in good correspondence with the theoretical propositions of the study and simulation results. The suggested evaluation metrics and optimization algorithms can be used in the design of advanced chaos-based communication systems with increased performance.

Digital chaotic systems used in various applications such as signal processing, artificial intelligence, and communications often suffer from the issue of dynamical degradation. This paper proposes a solution to address this problem in the digital tent map. Our proposed method includes a simple and optimized hardware architecture, along with a hardware-efficient perturbation method, to create a high-performance computing system that retains its chaotic properties. We implemented our proposed architecture using an FPGA (Field-Programmable Gate Array) and the 1’s complement fixed-point format. Our results demonstrate that the implemented digital circuit reduces logical resource consumption compared to state-of-the-art references and exhibits pseudo-random nature, as confirmed by various statistical tests. We validated our proposed pseudo-random number generator in a hardware architecture for particle swarm optimization, demonstrating its effectiveness.

Chaotic systems are attractive for digital and embedded applications due to their inherent unpredictability and sensitivity to initial conditions, making them suitable for applications such as image encryption. However, their implementation in digital hardware often suffers from dynamical degradation caused by limited numerical precision, leading to short periodic orbits and significantly reducing their effectiveness in security-related applications. Additionally, embedded systems impose strict constraints on hardware resources. To address these limitations, this work presents a hardware-efficient pseudorandom number generator (PRNG) based on a Sugeno-approximated sine map implementation with applications on image encryption, tailored for embedded systems based on field-programmable gate arrays (FPGAs). We first approximate the sine map using a lightweight Sugeno fuzzy inference system, replacing costly trigonometric operations and enabling implementation with only one addition unit and one multiplication unit; second, we introduce a perturbation mechanism to mitigate finite-precision degradation; third, the system performance is evaluated by comparing the use of posit numerical representation with the IEEE 754 floating-point standard; finally, we validate the design using the NIST SP 800-22 tests and demonstrate its applicability as a component in a secure image encryption scheme. The proposed PRNG combines statistical robustness with hardware efficiency, overcoming the typical trade-off faced by chaotic map implementations in digital systems. By balancing security strength and hardware efficiency, the proposed PRNG provides a promising solution for secure image encryption and has strong potential in emerging domains such as lightweight security applications.