Wide bandgap (WBG) power semiconductors are used in numerous power conversion applications because of their excellent switching characteristics. However, it is difficult to ensure short-circuit protection for WBG power semiconductors because of their shorter short-circuit withstand time. The fast-switching characteristics of WBG power semiconductors induces severe fluctuations in the drain-source voltage and drain current in switching transients, which results in the false triggering of the protection circuit. Therefore, the fast response speed and switching noise suppression are key requirements of the protection circuit for a WBG power semiconductor. To meet these requirements, an improved gate-voltage-driven desaturation protection circuit with a fast response speed and robust noise immunity is proposed in this study. The effect of switching noise on the proposed protection circuit is analyzed, and a detailed design procedure based on the analysis results is provided. The experimental results indicate that the protection delay of the proposed circuit is within 91 ns; additionally, the proposed circuit can survive switching noise during normal operation. Finally, the noise immunity analysis results are verified through experiments under various protection circuit parameter sets.

An LLC resonant converter should have high efficiency and power density. Further, it is important to reduce the volume and loss of the transformer, which provides insulation and voltage conversion between the input and output. When a planar core is used to achieve high power density, the magnitude of the parasitic components and the transformer loss considerably depend on the winding arrangement within the limited window area. Therefore, analyzing the various winding arrangements is necessary. To this end, an interleaved serpentine winding method that reduces the winding loss attributed to the high current by maximizing the window area of the planar core and has advantages of low parasitic capacitance and excellent assembly is proposed. The proposed winding method uses a Litz wire to reduce the DC copper loss, and it does not require additional space for the winding arrangement compared to that required by the U-type winding method. The capacitive energy distribution of the proposed winding method is compared with that of the existing U-type winding method to confirm the parasitic capacitance reduction effect of the proposed winding method. The formulae for calculating the effective capacitance of each winding method are derived for accurately estimating the parasitic capacitance. Finally, the effectiveness of the proposed analysis method and prototype are verified through finite element analysis simulation and experiments and it shows improvement of current waveforms and the overall efficiency increases about 0.5%.

Among the wide-bandgap devices, gallium nitride high electron mobility transistors (GaN HEMTs) are contributing to the high power density technology of power conversion systems due to their excellent physical properties. In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. In this paper, a parasitic inductance reduction design method for the stable driving of GaN HEMTs is proposed. To reduce parasitic inductance, we propose a vertical lattice loop structure having multiple loops, and this method can be applied regardless of the package type and shape of GaN HEMT. For the design of the proposed vertical lattice loop structure, the reference loop is defined to minimize leakage inductance and the identical loop is vertically stacked. The proposed structure is applied 6-layer PCB design example and verified by experimental results. Furthermore, the proposed design method is applied at the buck converter, and improved efficiency is verified from 600 kHz to 1MHz switching frequency.

Because SiC MOSFET-based zero-voltage switching (ZVS) power converter circuits provide high-speed switching, high power density and high efficiency can be achieved. However, an undesired negative spike is formed at the gate-source voltage owing to the crosstalk phenomenon in leg structures, such as half-bridge switch configurations, during high-speed switching. Additionally, ringing voltage occurs owing to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs have a lower gate voltage rating than conventional Si devices, it is essential to reduce the negative spike and ringing voltages to ensure reliability. In this paper, the gate driver circuit is proposed for reducing the negative spike and ringing voltages of the gate-source in ZVS circuits. Because the proposed gate driver circuit provides an effective impedance path for each section through an active switch, a stable driving voltage range of the gate-source can be achieved. To verify the proposed gate driver circuit, an accurate simulation model of the 3-pin SiC MOSFET package is proposed, and the validity of the proposed model is verified through comparison of the simulated waveforms with experimental waveforms. The performance of the proposed gate driver circuit is verified through PSpice simulation.

Wide bandgap (WBG) power semiconductors can achieve high efficiency and power density due to their low on-resistance and fast switching speeds. However, the fast-switching speed induces voltage to the parasitic inductance in the circuit, causing a significant overshoot in the drain-source voltage of the devices and the ringing of the drain current due to resonance with the parasitic capacitance. Thus, minimizing parasitic inductance is necessary for driving WBG power semiconductors in a stable manner. This paper proposes a three-dimensional lattice structure that reduces parasitic inductance through horizontal and vertical magnetic flux cancellations within a printed circuit board (PCB). The relationship between the magnetic flux cancellation and the parasitic inductance is analyzed, and the magnetic flux cancellation in the proposed structure is described. In addition, a practical PCB layout design procedure based on the proposed structure is provided. Simulation results demonstrate a 55.8% reduction in parasitic inductance, and experimental results show reduced overshoot and ringing at the switching transient, resulting in a 26% reduction in switching loss. As a result, the proposed method can improve the efficiency and stability of WBG device-based power converters.

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.