Compared to the conventional boost power factor correction (PFC) converter, a totem-pole bridgeless PFC has high efficiency because it does not have an input diode rectifier stage, but a current spike may occur when the polarity of the grid voltage changes. This paper proposes a digital control algorithm for bridgeless totem-pole PFC with a simple control structure based on the phase angle of grid voltage. The proposed algorithm has a PI-based double-loop control structure and performs DC-link voltage and input inductor current control. Rectifying switches operate based on the proposed rectification algorithm using phase angle information calculated through a single-phase phase-locked loop (PLL) to prevent current spikes. The feed-forward duty ratio value is calculated according to the polarity of the grid voltage and added to the double-loop controller to perform appropriate power factor control. The performance and feasibility of the proposed control algorithm are verified through a 3 kW hardware prototype.

High-frequency isolated LLC converters, which require both high efficiency and high density, are gaining important as pivotal technological challenges. In these converters, the transformer plays an essential role not only in providing galvanic isolation between the input and output and in facilitating voltage step-up and step-down but also as a key component in resonance. An appropriate design of the transformer size and structure is required to achieve both high efficiency and high density. This study introduces a self-equivalent magnetic model that incorporates the fringing effect, presenting a design methodology that utilizes this model. Compared with traditional transformer design methods, the proposed methodology allows for a more precise design by considering both the relative permeability and the magnetic path length (MPL), which represents the average path of the magnetic flux. In addition, we employ pareto optimal design techniques to extract a pareto set of transformer designs that satisfy specific conditions and, apply weighting factors to propose an optimal design. The feasibility of the proposed optimal transformer design methodology was verified through finite element analysis simulations and empirical tests using LLC converters.

Power factor correction (PFC) converters are utilized extensively across various applications, and therefore, developing customized control algorithms is essential to meet the diverse operational requirements. In critical conduction mode totem-pole PFC technology, introducing harmonic currents into a command signal is a viable approach for enhancing the performance of the PFC converter. However, this approach suffers from the risk of exceeding the planned harmonic current injection because of external interference. To overcome this issue, this article introduces a novel control algorithm that incorporates a harmonic injection technique to maintain stable performance despite disturbances or load variations. This algorithm uses Fourier analysis to precisely calculate each harmonic component and employs proportional-integral compensation along with feedforward corrections method to inject harmonic currents accurately in alignment with theoretical expectations. The efficacy of the proposed algorithm is validated through experiments conducted on a 350 W totem-pole PFC converter prototype under various load conditions. A comparison between the harmonic injection commands determined through a power analyzer and the actual measurements revealed that control was maintained within an error margin of 4.5%, demonstrating that harmonic control was effectively operational even under load variations.

Currently, wide bandgap (WBG) power semiconductor devices such as low-resistance SiC MOSFETs and GaN HEMTs are being utilized extensively to achieve high efficiency. However, securing a sufficient margin voltage between the drain–source sensing voltage and the trigger voltage of the device under test (DUT) during normal operation becomes challenging due to their low threshold voltage, thereby increasing the risk of incorrect detection. This study proposes an overcurrent detection circuit with high noise immunity for driving SiC MOSFETs in inverters and converters. The proposed circuit can detect not only short-circuit conditions but also overcurrent. Furthermore, this study presents a design approach for securing ample margin voltage between the drain–source sensing voltage and trigger voltage, validated through double pulse test (DPT), fault under load (FUL), and hard switching fault (HSF) experiments. The experimental results indicate that the proposed circuit secures margin voltage during normal operation and quickly deactivates the device in case of failure. Additionally, it was confirmed experimentally that the proposed circuit achieves a current sensing sensitivity of 92.667mV/A and can reliably detect faults within 35ns under FUL conditions and within 210ns under HSF conditions.

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

Active clamp forward (ACF) converters are being extensively applied to auxiliary power modules (APMs) in electric vehicles (EVs) to minimize the use of components and maximize efficiency. Existing ACF converter designs disregard the parasitic characteristics of the components and the leakage inductance of the transformer, resulting in design inaccuracies. This paper proposes a precise design method that considers the transformer impedance and parasitic characteristics of the components. Furthermore, the input–output relationship of the converter, stress on the switching components, and operational range are analyzed to introduce a design strategy that can minimize design errors. Moreover, this study implements a small-signal model and a controller design method based on the contrived model. The proposed design approach is validated through theoretical analysis, simulation comparison, and experimental verification, which includes the accuracy verification of the controller. This approach focuses on markedly reducing design errors, enhancing the precision of the ACF converter design, and further strengthening the reliability of converters for APM of an EV.