A delay generator is a timing control device that can generate a delay for the input signal according to the actual requirements. A delay generator with a combination of rough delay and precise delay is implemented on a Xilinx Kintex-7 series FPGA with a design scheme based on carry delay chain. The delay generator uses the delay time parameters sent by the upper monitor to work and to reflect the current working state to the upper monitor. In this article, a theoretical model of the delay generator is designed, and a delay compensation scheme is proposed to make the working state of the theoretical model closer to the actual circuit. Through simulation experiments, the time resolution of the delay generator is 54 ps, and the time accuracy is less than 50 ps. The delay scheme adopted in this article is highly scalable, and the time resolution and time accuracy can be further improved. Finally, a theoretical model of the delay generator with relatively high time resolution is implemented through low resource occupancy rate and little workload.

In order to seek a universal and simple test method to realize the embedded test of digital-analog mixed circuits, a new method based on D-M chaos model is proposed in this paper. First, starting with the characteristics of time series generated from a chaos model, the possible influence on the test results is analyzed. The D-M model not only has the characteristics of the discrete Tent (D-Tent) model, but also has a wide spectrum of signal sequences, and its correlation is small and close to the white noise. And then the model parameters are selected to generate the chaotic time series with optimal characteristics. Second, the test sequences of the analog circuit are constructed by the chaotic time series, and the simulation is carried out to load the vectors to the analog circuit, and the fault features of the output are analyzed. Finally, FPGA is adopted as an embedded controller of digital-analog mixed circuit tested object to validate the method. The results show that this proposed method can effectively identify the fault in digital-analog mixed circuits, and it has a great reference value to mixed circuit testing.