Long Short-Term Memory (LSTM) networks have been widely used to solve sequence modeling problems. For researchers, using LSTM networks as the core and combining it with pre-processing and post-processing to build complete algorithms is a general solution for solving sequence problems. As an ideal hardware platform for LSTM network inference, Field Programmable Gate Array (FPGA) with low power consumption and low latency characteristics can accelerate the execution of algorithms. However, implementing LSTM networks on FPGA requires specialized hardware and software knowledge and optimization skills, which is a challenge for researchers. To reduce the difficulty of deploying LSTM networks on FPGAs, we propose F-LSTM, an FPGA-based framework for heterogeneous computing. With the help of F-LSTM, researchers can quickly deploy LSTM-based algorithms to heterogeneous computing platforms. FPGA in the platform will automatically take up the computation of the LSTM network in the algorithm. At the same time, the CPU will perform the pre-processing and post-processing in the algorithm. To better design the algorithm, compress the model, and deploy the algorithm, we also propose a framework based on F-LSTM. The framework also integrates Pytorch to increase usability. Experimental results on sentiment analysis tasks show that deploying algorithms to the F-LSTM hardware platform can achieve a 1.8× performance improvement and a 5.4× energy efficiency improvement compared to GPU. Experimental results also validate the need to build heterogeneous computing systems. In conclusion, our work reduces the difficulty of deploying LSTM on FPGAs while guaranteeing algorithm performance compared to traditional work.

In this paper, we analyze the performance of a full-duplex (FD) cooperative non-orthogonal multiple access (C-NOMA) relaying system with an amplify-and-forward (AF) protocol in the presence of loopback interference in FD transceivers. Particularly, by considering channel estimation errors and quantization noise in low-resolution analog-to-digital converters (ADCs), the accurate approximation expression for the ergodic rate and closed-form solution for the outage probability are derived, respectively. The validity of the theoretical results is verified by Monte Carlo simulations, which show that both channel estimation errors and quantization noise have deleterious effects on ergodic rate and outage performance for moderate and high signal-to-noise ratios (SNR). In the second phase of the C-NOMA system, both the outage performance and ergodic sum rate decrease at high SNRs due to the effects of loop interference. When the ADC dynamic range reaches a certain level, the system performance is more affected by loopback interference and channel estimation errors compared to the quantization noise of the ADCs.