The Electrocardiogram (ECG) records are crucial for predicting heart diseases and evaluating patient’s health conditions. ECG signals provide essential peak values that reflect reliable health information. Analyzing ECG signals is a fundamental technique for computerized prediction with advancements in Very Large-Scale Integration (VLSI) technology and significantly impacts in biomedical signal processing. VLSI advancements focus on high-speed circuit functionality while minimizing power consumption and area occupancy. In ECG signal denoising, digital filters like Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) are commonly used. The FIR filters are preferred for their higher-order performance and stability over IIR filters, especially in real-time applications. The Modified FIR (MFIR) blocks were reconstructed using the optimized adder-multiplier block for better noise reduction performance. The MIT-BIT database is used as reference where the noises are filtered by the MFIR based on Optimized Kogge Stone Adder (OKSA). Features are extracted and analyzed using Discrete wavelet transform (DWT) and Cross Correlation (CC). At this modern era, Hybrid methods of Machine Learning (HMLM) methods are preferred because of their combined performance which is better than non-fused methods. The accuracy of the Hybrid Neural Network (HNN) model reached 92.3%, surpassing other models such as Generalized Sequential Neural Networks (GSNN), Artificial Neural Networks (ANN), Support Vector Machine with linear kernel (SVM linear), and Support Vector Machine with Radial Basis Function kernel (SVM RBF) by margins of 3.3%, 5.3%, 23.3%, and 24.3%, respectively. While the precision of the HNN is 91.1%, it was slightly lower than GSNN and ANN but higher than both SVM linear and SVM -RBF. The HNN with various features are incorporated to improve the ECG classification. The accuracy of the HNN is switched to 95.99% when the DWT and CC are combined. Also, it improvises other parameters such as precision 93.88%, recall is 0.94, F1 score is 0.88, Kappa is 0.89, kurtosis is 1.54, skewness is 1.52 and error rate 0.076. These parameters are higher than recently developed models whose algorithms and methods accuracy is more than 90%.

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C_in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

“The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. The bio medical signals are converted into IEEE 754 format as BIF. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. The main architecture is constructed using top level design with individual blocks defined as a part of it. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. By this process of FPU redefining, reduce the number of slice to 206 and increase the operating frequency of 46.12 MHz.

The modern day of communication world mainly focus on developing a highly organized architecture to perform high speed computation with minimum power consumption. The various architectures was developed to support computation in the fields like signal processing, data path communications, control and monitoring applications. To perform the high speed computation the architecture of Arithmetic logic unit (ALU) should be well organized in a manner to reduce power, area & propagation delay. The functional block of ALU is adder. This paper elaborates the analysis of different adder structure in terms of VLSI Parameters such as power, area and power delay product. The high speed computation are essential in mixed data processing applications and these computation are developed as blocks of FA to implement 16 bit of operations as a combination of ripple carry adder (RcA),carry skip (CSKA) and bernt kung adder(BkA). Those high speed adders produce the low value of propagation delay when it is implemented using this proposed architecture. The optimized structure of adders are developed by combining the effects of two adders which is functionally differed. The combined functionality of adder based on power & speed of computing The proposed methodology shows that power consumption is reduced by 43%, power delay product by 20.9 % and propagation delay by 46 % compared conventional method of analysis. and also provides the path to identify the effects of critical path delay and reduction it.

In the upswing of contemporary science we can monitor and regulate the saline flow rate. Scrupulous flow has to be retained so that risks of fore shortening the threshold level of patient’s heart rate, blood pressure and oxygen level in blood level. Intravenous infusion used intermittently in hospital has to be checked for is purity. For the change in threshold level of patient’s body condition, saline flow has to be adjusted. The assessments obtained from the patients is proceed to the centralizer controller which is connected to the cloud is updated periodically to avoid loss of reports. The updated data sets shared to the chemist and CPU so that flow rate of saline is controlled automatically in accordance to the data received. The machine learning based algorithm (SVM) is used to predict the more accurate changes on data which is obtained from patients so that the controller can act agilie. This work gives better results based on the accuracy level calculation and efficiency improvement in terms of more fast response.