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Prof. Donghyun Baek
Microwave Embedded Circuit & System (MECAS) Lab., School of Electrical Engineering, Chung-Ang University, 84 Heukseok-ro, Dongjack-gu, Seoul 06974, Korea

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Research Keywords & Expertise

0 Analog
0 RF
0 millimeter-wave
0 Mixed-mode circuit and system design for mobile communications
0 Radar sensors

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Analog
Radar sensors

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Journal article
Published: 10 May 2021 in Electronics
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A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is proposed to reduce the power consumption and compatibility with NMOS and PMOS injectors. The inductor-capacitor (LC) tank of the proposed CR-ILFM is designed with a fourth-order resonator using a transformer with distributed inductor to extend the locking range. The self-oscillated frequency of the proposed CR-ILFM is 23.82 GHz. The output frequency locking range is 17.8–34.8 GHz (64.6%) at a 0-dBm injection power without any additional control including supply voltage, varactor, and capacitor bank. The power consumption of the proposed CR-ILFM is 7.48 mW from a 1-V supply voltage and the die size is 0.75 mm × 0.45 mm. The CR-ILFM is implemented in a 65-nm CMOS technology.

ACS Style

Kwang-Il Oh; Goo-Han Ko; Gwang-Sub Kim; Jeong-Geun Kim; Donghyun Baek. A 17.8–34.8 GHz (64.6%) Locking Range Current-Reuse Injection-Locked Frequency Multiplier with Dual Injection Technique. Electronics 2021, 10, 1122 .

AMA Style

Kwang-Il Oh, Goo-Han Ko, Gwang-Sub Kim, Jeong-Geun Kim, Donghyun Baek. A 17.8–34.8 GHz (64.6%) Locking Range Current-Reuse Injection-Locked Frequency Multiplier with Dual Injection Technique. Electronics. 2021; 10 (9):1122.

Chicago/Turabian Style

Kwang-Il Oh; Goo-Han Ko; Gwang-Sub Kim; Jeong-Geun Kim; Donghyun Baek. 2021. "A 17.8–34.8 GHz (64.6%) Locking Range Current-Reuse Injection-Locked Frequency Multiplier with Dual Injection Technique." Electronics 10, no. 9: 1122.

Journal article
Published: 06 April 2021 in Sensors
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An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

ACS Style

Kwang-Il Oh; Goo-Han Ko; Jeong-Geun Kim; Donghyun Baek. An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications. Sensors 2021, 21, 2551 .

AMA Style

Kwang-Il Oh, Goo-Han Ko, Jeong-Geun Kim, Donghyun Baek. An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications. Sensors. 2021; 21 (7):2551.

Chicago/Turabian Style

Kwang-Il Oh; Goo-Han Ko; Jeong-Geun Kim; Donghyun Baek. 2021. "An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications." Sensors 21, no. 7: 2551.

Preprint
Published: 18 February 2021
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An 18.8–33.9-GHz, 2.26-mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1-V supply voltage. The entire die size is 0.75 mm ´ 0.45 mm. This CR-ILFD is implemented in a 65-nm CMOS technology.

ACS Style

Kwang-Il Oh; Goo-Han Ko; Jeong-Geun Kim; Donghyun Baek. An 18.8–33.9-GHz, 2.26-mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications. 2021, 1 .

AMA Style

Kwang-Il Oh, Goo-Han Ko, Jeong-Geun Kim, Donghyun Baek. An 18.8–33.9-GHz, 2.26-mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications. . 2021; ():1.

Chicago/Turabian Style

Kwang-Il Oh; Goo-Han Ko; Jeong-Geun Kim; Donghyun Baek. 2021. "An 18.8–33.9-GHz, 2.26-mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications." , no. : 1.

Journal article
Published: 14 August 2020 in IEEE Access
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In this paper, a fully-integrated dual-mode X-band radar transceiver that supports Doppler radar and frequency modulated continuous wave (FMCW) radar is proposed. To remove large off-chip DC-blocking capacitors in the Doppler mode, the double-conversion technique and local oscillator (LO) chopping technique are introduced. These techniques remove the DC offset and makes the transceiver more robust to the TX to RX leakage. In addition, they also improve the noise figure (NF) by filtering out 1/f noise of the analog baseband. The FMCW radar is realized using a direct-conversion receiver and a chirp generator. The chirp generator consists of a frequency sweep generator (FSG) and a fractional-N phase-locked loop (PLL). All the analog baseband components including a programable gain amplifiers (PGA) and 1/R4 range compensation filters are integrated on the chip as well as a bandgap and low-dropout regulators. The operating frequency is from 9.7 to 12.3 GHz, which consumes 216 mW in Doppler mode and 201.6 mW in FMCW mode from a 1.2-V supply voltage. The maximum chirp bandwidth is 750 MHz and the maximum receiver gain is 76 dB with 6-dB gain step. The chip size of the transceiver is 7.68 mm2 including all the pads.

ACS Style

Keum-Won Ha; Jeong-Yun Lee; Goo-Han Ko; Young-Jin Kim; Jeong-Geun Kim; Donghyun Baek. Fully Integrated Dual-Mode X-Band Radar Transceiver Using Configurable Receiver and Local Oscillator. IEEE Access 2020, 8, 151403 -151414.

AMA Style

Keum-Won Ha, Jeong-Yun Lee, Goo-Han Ko, Young-Jin Kim, Jeong-Geun Kim, Donghyun Baek. Fully Integrated Dual-Mode X-Band Radar Transceiver Using Configurable Receiver and Local Oscillator. IEEE Access. 2020; 8 (99):151403-151414.

Chicago/Turabian Style

Keum-Won Ha; Jeong-Yun Lee; Goo-Han Ko; Young-Jin Kim; Jeong-Geun Kim; Donghyun Baek. 2020. "Fully Integrated Dual-Mode X-Band Radar Transceiver Using Configurable Receiver and Local Oscillator." IEEE Access 8, no. 99: 151403-151414.

Journal article
Published: 11 August 2020 in Electronics
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This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.

ACS Style

Jeong-Yun Lee; Gwang Sub Kim; Goo-Han Ko; Kwang-Il Oh; Jae Gyeong Park; Donghyun Baek. Low Phase Noise and Wide-Range Class-C VCO Using Auto-Adaptive Bias Technique. Electronics 2020, 9, 1290 .

AMA Style

Jeong-Yun Lee, Gwang Sub Kim, Goo-Han Ko, Kwang-Il Oh, Jae Gyeong Park, Donghyun Baek. Low Phase Noise and Wide-Range Class-C VCO Using Auto-Adaptive Bias Technique. Electronics. 2020; 9 (8):1290.

Chicago/Turabian Style

Jeong-Yun Lee; Gwang Sub Kim; Goo-Han Ko; Kwang-Il Oh; Jae Gyeong Park; Donghyun Baek. 2020. "Low Phase Noise and Wide-Range Class-C VCO Using Auto-Adaptive Bias Technique." Electronics 9, no. 8: 1290.

Journal article
Published: 19 July 2019 in IEEE Access
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In this paper, an output capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) is implemented. To increase the current efficiency, low quiescent current less than 10 μA is used. The stability problem arising from the low bias current is overcome by applying two kinds of compensation methods. By drawing the pole-zero plot using the open-loop transfer function obtained by the small-signal modeling, the stability of the proposed LDO is guaranteed to be less than 70 mA. By using the proposed compensation methods, two zeros of the right-half plane (RHP) can be placed in the left-half plane (LHP) to prevent lagging and reduce the on-chip compensation capacitor. The current efficiency of the proposed LDO is 99.99% at the load current of 70 mA.

ACS Style

Gwang Sub Kim; Jae Kyung Park; Goo-Han Ko; Donghyun Baek. Capacitor-Less Low-Dropout (LDO) Regulator With 99.99% Current Efficiency Using Active Feedforward and Reverse Nested Miller Compensations. IEEE Access 2019, 7, 98630 -98638.

AMA Style

Gwang Sub Kim, Jae Kyung Park, Goo-Han Ko, Donghyun Baek. Capacitor-Less Low-Dropout (LDO) Regulator With 99.99% Current Efficiency Using Active Feedforward and Reverse Nested Miller Compensations. IEEE Access. 2019; 7 ():98630-98638.

Chicago/Turabian Style

Gwang Sub Kim; Jae Kyung Park; Goo-Han Ko; Donghyun Baek. 2019. "Capacitor-Less Low-Dropout (LDO) Regulator With 99.99% Current Efficiency Using Active Feedforward and Reverse Nested Miller Compensations." IEEE Access 7, no. : 98630-98638.

Journal article
Published: 16 January 2019 in Electronics
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In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 μA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.

ACS Style

Jeong-Yun Lee; Gwang-Sub Kim; Kwang-Il Oh; Donghyun Baek. Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator. Electronics 2019, 8, 98 .

AMA Style

Jeong-Yun Lee, Gwang-Sub Kim, Kwang-Il Oh, Donghyun Baek. Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator. Electronics. 2019; 8 (1):98.

Chicago/Turabian Style

Jeong-Yun Lee; Gwang-Sub Kim; Kwang-Il Oh; Donghyun Baek. 2019. "Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator." Electronics 8, no. 1: 98.

Journal article
Published: 01 April 2018 in Sensors
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Recently, studies have been actively carried out to implement motion detecting sensors by applying radar techniques. Doppler radar or frequency-modulated continuous wave (FMCW) radar are mainly used, but each type has drawbacks. In Doppler radar, no signal is detected when the movement is stopped. Also, FMCW radar cannot function when the detection object is near the sensor. Therefore, by implementing a single continuous wave (CW) radar for operating in dual-mode, the disadvantages in each mode can be compensated for. In this paper, a dual mode local oscillator (LO) is proposed that makes a CW radar operate as a Doppler or FMCW radar. To make the dual-mode LO, a method that controls the division ratio of the phase locked loop (PLL) is used. To support both radar mode easily, the proposed LO is implemented by adding a frequency sweep generator (FSG) block to a fractional-N PLL. The operation mode of the LO is determined by according to whether this block is operating or not. Since most radar sensors are used in conjunction with microcontroller units (MCUs), the proposed architecture is capable of dual-mode operation by changing only the input control code. In addition, all components such as VCO, LDO, and loop filter are integrated into the chip, so complexity and interface issues can be solved when implementing radar sensors. Thus, the proposed dual-mode LO is suitable as a radar sensor.

ACS Style

Keum-Won Ha; Jeong-Yun Lee; Jeong-Geun Kim; Donghyun Baek. Design of Dual-Mode Local Oscillators Using CMOS Technology for Motion Detection Sensors. Sensors 2018, 18, 1057 .

AMA Style

Keum-Won Ha, Jeong-Yun Lee, Jeong-Geun Kim, Donghyun Baek. Design of Dual-Mode Local Oscillators Using CMOS Technology for Motion Detection Sensors. Sensors. 2018; 18 (4):1057.

Chicago/Turabian Style

Keum-Won Ha; Jeong-Yun Lee; Jeong-Geun Kim; Donghyun Baek. 2018. "Design of Dual-Mode Local Oscillators Using CMOS Technology for Motion Detection Sensors." Sensors 18, no. 4: 1057.

Journal article
Published: 19 March 2018 in Energies
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In this paper, output capacitor-less low-dropout (LDO) regulator using active-feedback and current-reuse feedforward compensation (AFCFC) is presented. The open-loop transfer function was obtained using small-signal modeling. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulations that the stability was ensured under the load current of 50 mA. The proposed compensation method increases gain-bandwidth product (GBW) and reduces the on-chip compensation capacitor. The proposed AFCFC technique was applied to a three-stage output capacitor-less LDO. The LDO has a GBW of 5.6 MHz with a small on-chip capacitor of 2.6 pF. Fast-transient time of 450 ns with low quiescent current of 65.8 μA was achieved. The LDO was fabricated in 130 nm CMOS process consuming 180 × 140 μm2 of the silicon area.

ACS Style

Eun-Taek Sung; Sangyong Park; Donghyun Baek. A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation. Energies 2018, 11, 688 .

AMA Style

Eun-Taek Sung, Sangyong Park, Donghyun Baek. A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation. Energies. 2018; 11 (3):688.

Chicago/Turabian Style

Eun-Taek Sung; Sangyong Park; Donghyun Baek. 2018. "A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation." Energies 11, no. 3: 688.

Journal article
Published: 29 January 2018 in Applied Sciences
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This paper presents two single-pole, double-throw (SPDT) mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS) process. One switch employs cross-biasing (CB) control with a single supply, while the other uses dual-supply biasing (DSB) control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs) in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX) and receiver (RX), as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF) switch is 260 μm × 230 μm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3) of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

ACS Style

Sangyong Park; Jeong-Yun Lee; Jong-Yeon Lee; Jong-Ryul Yang; Donghyun Beak. 25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver. Applied Sciences 2018, 8, 196 .

AMA Style

Sangyong Park, Jeong-Yun Lee, Jong-Yeon Lee, Jong-Ryul Yang, Donghyun Beak. 25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver. Applied Sciences. 2018; 8 (2):196.

Chicago/Turabian Style

Sangyong Park; Jeong-Yun Lee; Jong-Yeon Lee; Jong-Ryul Yang; Donghyun Beak. 2018. "25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver." Applied Sciences 8, no. 2: 196.

Journal article
Published: 31 October 2017 in JSTS:Journal of Semiconductor Technology and Science
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ACS Style

Jae-Kyung Lee; Donghyun Baek; Young-Jin Kim. IIP2-improved Frontend Receiver using a Mismatch Compensation LNA. JSTS:Journal of Semiconductor Technology and Science 2017, 17, 603 -610.

AMA Style

Jae-Kyung Lee, Donghyun Baek, Young-Jin Kim. IIP2-improved Frontend Receiver using a Mismatch Compensation LNA. JSTS:Journal of Semiconductor Technology and Science. 2017; 17 (5):603-610.

Chicago/Turabian Style

Jae-Kyung Lee; Donghyun Baek; Young-Jin Kim. 2017. "IIP2-improved Frontend Receiver using a Mismatch Compensation LNA." JSTS:Journal of Semiconductor Technology and Science 17, no. 5: 603-610.

Journal article
Published: 09 September 2017 in Sensors
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We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

ACS Style

Jong-Ryul Yang; Seong-Tae Han; Donghyun Baek. Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier. Sensors 2017, 17, 2069 .

AMA Style

Jong-Ryul Yang, Seong-Tae Han, Donghyun Baek. Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier. Sensors. 2017; 17 (9):2069.

Chicago/Turabian Style

Jong-Ryul Yang; Seong-Tae Han; Donghyun Baek. 2017. "Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier." Sensors 17, no. 9: 2069.

Proceedings article
Published: 01 August 2017 in 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
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This paper presents a dual-mode signal generator using a fractional-N phase locked loop (PLL) and frequency-sweep modulator (FSM) for X-band Doppler and frequency modulated continuous wave (FMCW) radar sensor applications. The key function of the proposed structure is a frequency sweep modulator (FSM), which changes the PLL division ratio to sweep output frequency according to the input control code. Thus, the proposed signal generator is easy to accommodate both Doppler and FMCW modes, simultaneously. The proposed dual-mode signal generator is realized using a 1P8M 0.13 μm CMOS process. The chip size is 1.45 mm2 excluding all the pads, and consumes 114 mW from a 1.2-V supply voltage. The output frequency range of the proposed PLL is from 9.7 to 12.4 GHz which covers X-band radar sensor application band. The output power of the proposed structure is uniformly transmitted within the allocated frequency range in FMCW mode. The phase noise is -78 dBc/Hz at 10-kHz offset at the frequency of 10.525 GHz, and -126.78 dBc/Hz at 25-MHz offset frequency.

ACS Style

Keum-Won Ha; Jeong-Yun Lee; Sangyong Park; Donghyun Baek. A dual-mode signal generator using PLL for X-band radar sensor applications. 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) 2017, 4 -6.

AMA Style

Keum-Won Ha, Jeong-Yun Lee, Sangyong Park, Donghyun Baek. A dual-mode signal generator using PLL for X-band radar sensor applications. 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). 2017; ():4-6.

Chicago/Turabian Style

Keum-Won Ha; Jeong-Yun Lee; Sangyong Park; Donghyun Baek. 2017. "A dual-mode signal generator using PLL for X-band radar sensor applications." 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) , no. : 4-6.

Journal article
Published: 19 April 2017 in IEEE Transactions on Microwave Theory and Techniques
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This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13-μm standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain-source current nonlinearity. This also reduces distortions due to drain-source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM-AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a -35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

ACS Style

Seunghoon Kang; Donghyun Baek; Songcheol Hong. A 5-GHz WLAN RF CMOS Power Amplifier With a Parallel-Cascoded Configuration and an Active Feedback Linearizer. IEEE Transactions on Microwave Theory and Techniques 2017, 65, 3230 -3244.

AMA Style

Seunghoon Kang, Donghyun Baek, Songcheol Hong. A 5-GHz WLAN RF CMOS Power Amplifier With a Parallel-Cascoded Configuration and an Active Feedback Linearizer. IEEE Transactions on Microwave Theory and Techniques. 2017; 65 (9):3230-3244.

Chicago/Turabian Style

Seunghoon Kang; Donghyun Baek; Songcheol Hong. 2017. "A 5-GHz WLAN RF CMOS Power Amplifier With a Parallel-Cascoded Configuration and an Active Feedback Linearizer." IEEE Transactions on Microwave Theory and Techniques 65, no. 9: 3230-3244.

Journal article
Published: 28 February 2017 in JSTS:Journal of Semiconductor Technology and Science
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ACS Style

Hyuk Ryu; Keum-Won Ha; Eun-Taek Sung; Donghyun Baek. Low Phase Noise Series-coupled VCO using Current-reuse and Armstrong Topologies. JSTS:Journal of Semiconductor Technology and Science 2017, 17, 42 -47.

AMA Style

Hyuk Ryu, Keum-Won Ha, Eun-Taek Sung, Donghyun Baek. Low Phase Noise Series-coupled VCO using Current-reuse and Armstrong Topologies. JSTS:Journal of Semiconductor Technology and Science. 2017; 17 (1):42-47.

Chicago/Turabian Style

Hyuk Ryu; Keum-Won Ha; Eun-Taek Sung; Donghyun Baek. 2017. "Low Phase Noise Series-coupled VCO using Current-reuse and Armstrong Topologies." JSTS:Journal of Semiconductor Technology and Science 17, no. 1: 42-47.

Journal article
Published: 02 December 2016 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary frequency search algorithm (B-FSA), where the frequency search time per cycle is fixed. This eliminates unnecessary clocking times during the frequency comparison process, and thus reduces the total PLL lock time. The additional circuitry needed for A-FSA is only a simple counter controller, thus minimizing hardware overhead. To verify the effectiveness of the proposed algorithm, two wideband PLLs are designed and simulated using a 65-nm CMOS technology: one with B-FSA, and the other with A-FSA. The latter achieves a lock time faster than the former by at least a factor of 2, even under worst case conditions.

ACS Style

Hyuk Ryu; Eun-Taek Sung; Sangyong Park; Je-Kwang Cho; Donghyun Baek. Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016, 25, 1490 -1496.

AMA Style

Hyuk Ryu, Eun-Taek Sung, Sangyong Park, Je-Kwang Cho, Donghyun Baek. Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016; 25 (4):1490-1496.

Chicago/Turabian Style

Hyuk Ryu; Eun-Taek Sung; Sangyong Park; Je-Kwang Cho; Donghyun Baek. 2016. "Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4: 1490-1496.

Article
Published: 06 September 2016 in Analog Integrated Circuits and Signal Processing
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In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta (\(\varSigma \varDelta\)) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order \(\varSigma \varDelta\) modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.

ACS Style

Je-Kwang Cho; Donghyun Baek. Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators. Analog Integrated Circuits and Signal Processing 2016, 90, 55 -63.

AMA Style

Je-Kwang Cho, Donghyun Baek. Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators. Analog Integrated Circuits and Signal Processing. 2016; 90 (1):55-63.

Chicago/Turabian Style

Je-Kwang Cho; Donghyun Baek. 2016. "Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators." Analog Integrated Circuits and Signal Processing 90, no. 1: 55-63.

Journal article
Published: 30 August 2016 in JSTS:Journal of Semiconductor Technology and Science
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ACS Style

Jang-Hoon Han; Jeong-Geun Kim; Donghyun Baek. X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology. JSTS:Journal of Semiconductor Technology and Science 2016, 16, 511 -519.

AMA Style

Jang-Hoon Han, Jeong-Geun Kim, Donghyun Baek. X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology. JSTS:Journal of Semiconductor Technology and Science. 2016; 16 (4):511-519.

Chicago/Turabian Style

Jang-Hoon Han; Jeong-Geun Kim; Donghyun Baek. 2016. "X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology." JSTS:Journal of Semiconductor Technology and Science 16, no. 4: 511-519.

Article
Published: 12 April 2016 in ETRI Journal
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This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-μm silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is 0.93?mm0.68?mm, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

ACS Style

Moon‐Kyu Cho; Jeong‐Geun Kim; Donghyun Baek. A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-?#x3BC;m SOI CMOS Technology. ETRI Journal 2016, 35, 638 -643.

AMA Style

Moon‐Kyu Cho, Jeong‐Geun Kim, Donghyun Baek. A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-?#x3BC;m SOI CMOS Technology. ETRI Journal. 2016; 35 (4):638-643.

Chicago/Turabian Style

Moon‐Kyu Cho; Jeong‐Geun Kim; Donghyun Baek. 2016. "A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-?#x3BC;m SOI CMOS Technology." ETRI Journal 35, no. 4: 638-643.

Journal article
Published: 25 February 2016 in Journal of the Institute of Electronics and Information Engineers
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본 논문에서는 위상고정루프를 이용한 낮은 지터 성능을 갖는 스마트 오디오 디바이스용 이중출력 주파수 합성기를 제안하였다. 제안하는 주파수 합성기는 1.8 V 동부 0.18-㎛ CMOS 공정을 이용하여 설계하였다. 다양한 오디오 샘플링 주파수를 출력하기 위해 3차 시그마-델타 모듈레이션을 이용하여 fraction-N 디바이더를 설계하였다. 오디오 반도체에서 요구되는 낮은 지터 성능을 만족 시키기 위해 인-밴드 잡음을 분석, 최적화 하였다. 0.6 ㎟의 칩 사이즈를 가지고 0.6 MHz―200 MHz의 출력 주파수를 갖는다. 모든 모드에서 측정된 지터는 11.4 ps―21.6 ps 이다.

ACS Style

Ye-Seul Baek; Jeong-Yun Lee; Hyuk Ryu; JongYeon Lee; Donghyun Baek. A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices. Journal of the Institute of Electronics and Information Engineers 2016, 53, 27 -35.

AMA Style

Ye-Seul Baek, Jeong-Yun Lee, Hyuk Ryu, JongYeon Lee, Donghyun Baek. A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices. Journal of the Institute of Electronics and Information Engineers. 2016; 53 (2):27-35.

Chicago/Turabian Style

Ye-Seul Baek; Jeong-Yun Lee; Hyuk Ryu; JongYeon Lee; Donghyun Baek. 2016. "A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices." Journal of the Institute of Electronics and Information Engineers 53, no. 2: 27-35.