A fully integrated quadrature VCO at 8 GHz is presented. The VCO is implemented using a transformer-based LC tank in 0.18 μm CMOS technology, in which two VCOs are coupled to generate I-Q signals. The VCO is realized employing the drain-gate transformer feedback configuration proposed here. This makes use of the quality factor enhancement in the resonator using a transformer and the deep switching-off technique by controlling gate bias. By turning off switching transistors of the differential VCO core deeply, the phase noise performance is improved more than 10 dB. The measured phase noise values are -110 and -117 dBc/HZ at the offset frequencies of 600 kHz and 1 MHz respectively. The tuning range of 250 MHz is achieved with the control voltage from 0 to 1 V. The VCO draws 8 mA in two differential core circuits from 3 V supply. When the bias voltage goes down to 2.5 V, the phase noise decrease only 2 dB compared to that of 3 V bias. The VCO performances are compared with previously reported quadrature Si VCOs in 5/spl sim/12 GHz frequency range.

In this paper, we propose a circularly polarized balanced radar front-end topology with a Tx leakage canceller. This radar is composed of a dual-orthogonal fed microstrip patch antenna, a 90deg delay line, a differential cross-coupled oscillator, two Lange couplers, a Wilkinson combiner, and a mixer. We implemented circularly polarized balanced Doppler radars by using a printed circuit board and InGaP/GaAs heterojunction bipolar transistor technologies. The front-end chip and module with antenna are 1 mm times 1 mm and 3 cm times 3 cm, respectively. The average Tx-to-Rx isolation is about 36 dB. This radar can measure speeds as low as 0.5 mm/s, which corresponds to a 0.076-Hz Doppler shift. The received signals of the circularly polarized balanced Doppler radar are about two times larger than those of a linearly polarized balanced Doppler radar due to the topology. This result occurs because the proposed radar has an intrinsic loss of only 3 dB in the receiving path.

This letter presents a 5 b phase shifter using a commercial 0.18 $\mu{\rm m}$ SOI process for X-band phased array antenna. The phase coverage of 360$^{\circ}$ with the LSB of 11.25$^{\circ}$ is achieved at 8–12 GHz. The RMS phase error and amplitude variation are less than 6.5$^{\circ}$ and 0.5 dB, respectively. The measured insertion loss is less than 10.8 dB, and the input and output return losses are over 12 dB at 8–12 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.14\times 0.78\ {\rm mm}^{2}$ excluding pads. To the authors' knowledge, this is the first demonstration of X-band phase shifter using a commercial SOI technology.

A dual band voltage-controlled oscillator (VCO) that can cover 13- and 22-GHz bands is proposed and implemented using an InGaP/GaAs heterojunction bipolar transistor (HBT) technology. The frequency band is selected by mode switching between differential mode at low frequency and common mode at high frequency. The differential mode means that voltages appearing at two tank ports have opposite polarities and the common mode, the same polarities. Mode switching allows the VCO to operate at two resonant frequencies with a single LC tank. The measured phase-noise performances of a dual band VCO are -108 and -106 dBc/Hz at 1 MHz offset at the frequencies of 13 and 22 GHz, respectively, while drawing 22 mA and 16 mA from a 4-V supply. Switching times between two bands are less than 24 ns.

In this paper, an output capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) is implemented. To increase the current efficiency, low quiescent current less than 10 μA is used. The stability problem arising from the low bias current is overcome by applying two kinds of compensation methods. By drawing the pole-zero plot using the open-loop transfer function obtained by the small-signal modeling, the stability of the proposed LDO is guaranteed to be less than 70 mA. By using the proposed compensation methods, two zeros of the right-half plane (RHP) can be placed in the left-half plane (LHP) to prevent lagging and reduce the on-chip compensation capacitor. The current efficiency of the proposed LDO is 99.99% at the load current of 70 mA.

In this letter, a new complementary Hartley (C-Hartley) voltage controlled oscillator (VCO) with fully differential outputs is proposed, in which the self-biasing configuration is introduced to solve the biasing difficulty of a Hartley VCO by employing a five-port transformer. The proposed C-Hartley VCO with the center frequency of 5.6 GHz is implemented in a 1P6M 0.18 μm CMOS process. The measurement result shows that the phase noise is -123.6 dBc/Hz at 1 MHz offset frequency, while dissipating 6.5 mA from 1.6 V supply with the FOM of -188.5 dBc.