This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

This paper presents the design of a Delay-Locked Loop (DLL) with a simple architecture and a wide input clock duty cycle range. The design is tailored to meet the increasing data rate and stringent clock requirements of modern semiconductor chips, with particular applicability to dynamic random-access memory (DRAM) systems. The structure features two Bang-Bang Phase Detectors (BBPDs) to adjust the rising and falling edges of the divided clock. Implemented using a 65 nm CMOS process, the design was verified through simulation. At a working frequency of 3.2 GHz, the input clock duty cycle range spans from 18% to 72%, with a maximum output clock duty cycle error of just 0.6%, a peak-to-peak jitter of 15.73 ps, and a power consumption of 12.7 mW.